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Input Fields and Allowable Ranges
Attenuation:
RF In:
RF Out:
Network Config:
Date/Time:
Firmware:
Update:
New Firmware:
Configuration:
MS Power Class:
Condition
PWR CNTL
High:
Mid:
Low:
Manual Test:
Averaging:
RF Output:
BS Level:
BER BS Level:
BER Frames:
Loopback Delay:
Limit Setting:
Peak TX Power
PWR CNTL
Burst Timing:
Power Ramp:
Phase Error
RMS/Peak:
Frequency Error:
BER:
FER:
BLER:
RX Quality:
RX Level:
DC Current
Camp On:
Talk:
192
0 to 999 (MCC), 0 to 99 (MNC), 0 to 7 (NCC), 0 to 65535 (NCC), 2 to 9 (BS_PA)
1990 to 2089 (YYYY), 01 to 12 (MM), 01 to 31 (DD)
2 to 5
2: +39 dBm to
19: +5 dBm
1 to 13000 frames in 1 frame steps [# of bits shown]
:
Template, or 99.9 to +99.9 dB in 0.1 dB steps
a
2: +39 dBm to
19: +5 dBm
0: < 0.2%, 1: 0.2 to 0.4%, ..., 6: 6.4 to 12.8%, 7: > 12.8%
0: < 110 dBm, 1: 110 to 109 dBm, ..., 62: 49 to 48 dBm, 63: > 48
Off, On
0.0 to 99.9 dB in 0.1 dB steps
0.0 to 99.5 dB in 0.5 dB steps
00 to 23 (HH), 00 to 59 (MM)
X.XX.XX
Off, On
Y.YY.YY [when Update is On]
1 to 3
29: +36 dBm to
31: +32 dBm,
0: +30 dBm to
15: 0 dBm
Off, 2 to 99
Auto, On
110.0 to 50.0 dBm in 0.5 dB steps
110.0 to 50.0 dBm in 0.5 dB steps
Short, Mid, Long
29: +36 dBm to
31: +32 dBm,
0: +30 dBm to
15: 0 dBm
9.9 to +9.9 bits in 0.1 bit steps
Template
0.0 to 99.9 ° in 0.1 ° steps
999 to + 999 Hz in 1 Hz steps
0.00 to 99.99% in 0.01% steps
0.00 to 99.99% in 0.01% steps
0.00 to 99.99% in 0.01% steps
3 to 1000 mA in 1 mA steps
3 to 1000 mA in 1 mA steps
1 to 3
30 +33 dBm to
31: +32 dBm,
0: +30 dBm to
15: 0 dBm
30 +33 dBm to
31: +32 dBm,
0: +30 dBm to
15: 0 dBm
Appendix B
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