Test J / K; Test Method With Evaluation Board; Test Environment - Epson S2R72A21 Application Note

HS Test
Packet
HS Host
4. Please acquire the HS eye Pattern from the connected Host Test Fixture on procedure-3 using the
oscilloscope.
6.2.2

Test J / K

Here is the explanation of the S2R72A21's output methods of High-speed J/K. It is similar to the method
explained on section 6.2.1. Please make the Host output the High-Speed J/K via Test J/K mode instead of Test
Packet.
1. Please connect the HS Host to the INT port and HS Device to the EXT port and confirm whether the Host
and Device is HS connected. Please avoid the Bus to be Suspend or FS/LS condition after connection.
Herewith the S2R72A21 would be HS state.
2. Please make the HS Host into Test J/K mode and input the Test J/K signal from the Host to the INT port.
Herewith the S2R72A21 would output the High speed J/K from the EXT port.
3. Please measure the voltage level using the High-speed J/K signal which is output from the EXT port.
When doing another testing after Test_J / K output, please either set the ENABLE pin or XRESET pin of
S2R72A21 0>1 or turn off the HVDD power and supply again.
6.3

Test method with Evaluation board

Here are the test method procedure examples using the S2R72A21 evaluation board (S5U2R72A11F0100 /
Onnetoh) and the PC which installed the "USB High-Speed Electrical Test Tool".
6.3.1

Test environment

The test environment overview is below.
Host PC
22
S2R72A21
HS Test
Packet
INT_DP EXT_DP
INT_DM EXT_DM
Figure 6.2.1.2
S2R72A21 Board
A11
Seiko Epson Corporation
Host Test Fixture
Procedure-3 connection
HS USB memory
Test Fixture
Oscilloscope
SMA cable
Oscilloscope
SMA cable
S2R72A21 Application Note
(Rev.1.00)