Reading The Status Register; Interrupts - Agilent Technologies 3458A User Manual

Reading the Status
Register

Interrupts

1. Bits 4, 5, and 6 are not cleared if the conditions(s) that set the bit(s) still exist.
which removed the error bit but left bit 6 set,
Bit 7 (weight = 128) Data Available--a reading or query response is
available in the output buffer.
The STB? query command reads the status register and returns the weighted
sum of all set bits. The STB? command does not clear the status register. The
following program uses the STB? command to read the contents of the status
register.
10 OUTPUT 722."STB?"
20 ENTER 722; A
30 PRINT A
40 END
For example, assume bit 3 (weight = 8) and bit 7 (weight = 128) are set. The
above program returns the sum of the two weights (136).
The STB? command will never reveal bit 4 (Ready for Instructions) set
because the multimeter is busy processing the STB? command and, therefore,
is not ready. If you intend to monitor the ready bit, you must use the GPIB
Serial Poll command to read the status register. If the SRQ line is true, the
Serial Poll command clears all status register bits.* The SRQ line is also
returned to false if bit 6 is cleared. If the SRQ line is false during Serial Poll,
the register's contents are not changed. The following program shows how
to read the status register using the Serial Poll command.
10 P=SPOLL(722)
20 DISP P
30 END
To clear the status register,
OUTPUT 722; "CSB"
When a bit of the status register is set and has been enabled to assert SRQ
(RQS command), the multimeter sets the GPIB SRQ line true. This can be
used to alert the controller to interrupt its present operation and find out what
service the multimeter requires. (Refer to your controller-operating manual
for information on how to program it to respond to the interrupt.)
To allow any of the status register bits to set the SRQ line true, you must first
enable the bit(s) with the RQS command. For example, suppose your
application requires an interrupt when a high or low limit is exceeded (bit 1),
power is cycled (bit 3), or when an error occurs (bit 5). The decimal
equivalents of these bits are 2, 8, and 32, respectively. The decimal sum is
42. You can enable these bits to assert SRQ by sending:
OUTPUT 722;"RQS 42"
Now, whenever one of the events associated with bits 1, 3, or 5 occurs, it will
set bit 6 in the status register and assert SRQ. Notice that the bits that are not
1
send:
Chapter 3 Configuring for Measurements 77