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Electrical Specifications
Table 16.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
L
L
L
L
H
H
H
H
2.8.3
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. See
2.8.4
BCLK[1:0] Specifications
Table 17.
Front Side Bus Differential BCLK Specifications
Symbol
V
L
V
H
V
CROSS(abs)
V
CROSS
V
OS
V
US
V
SWING
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3.
"Steady state" voltage, not including overshoot or undershoot.
4.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
5.
Measurement taken from differential waveform.
Datasheet
BSEL1
BSEL0
L
L
L
H
H
H
H
L
H
L
H
H
L
H
L
L
Table 4
for DC specifications.
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Range of Crossing Points
Overshoot
Undershoot
Differential Output Swing
FSB Frequency
266 MHz
Reserved
Reserved
200 MHz
Reserved
Reserved
Reserved
Reserved
Min
Typ
Max
-0.30
N/A
N/A
N/A
N/A
1.15
0.300
N/A
0.550
N/A
N/A
0.140
N/A
N/A
1.4
-0.300
N/A
N/A
0.300
N/A
N/A
1
Unit
Figure
Notes
V
3
V
3
V
3
2
V
3
-
V
3
3
V
3
3
V
4
4
29
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