Phase Lock Loop (Pll) And Filter; Bclk[1:0] Specifications (Ck505 Based Platforms); Bsel[2:0] Frequency Table For Bclk[1:0]; Front Side Bus Differential Bclk Specifications - Intel CORE 2 DUO E4000 - DATASHEET 3-2008 Datasheet

Table 16.

BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2
L
L
L
L
H
H
H
H
2.7.7

Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to
2.7.8

BCLK[1:0] Specifications (CK505 based Platforms)

Table 17.

Front Side Bus Differential BCLK Specifications

Symbol
V
L
V
H
V
CROSS(abs)
ΔV
CROSS
V
OS
V
US
V
SWING
I
LI
Cpad
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. "Steady state" voltage, not including overshoot or undershoot.
3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0
equals the falling edge of BCLK1.
4. V is the statistical average of the V
Havg
5. The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as
the absolute value of the minimum voltage.
7. Measurement taken from differential waveform.
8. Cpad includes die capacitance only. No package parasitics are included.
30
BSEL1 BSEL0
L L
L H
H H
H L
H L
H H
L H
L L
Table 5 for DC specifications.
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Range of Crossing Points
Overshoot
Undershoot
Differential Output Swing
Input Leakage Current
Pad Capacitance
FSB Frequency
266 MHz
RESERVED
RESERVED
200 MHz
RESERVED
RESERVED
RESERVED
333 MHz
Min Typ Max
-0.30 N/A N/A
N/A N/A 1.15
0.300 N/A 0.550
N/A N/A 0.140
N/A N/A 1.4
-0.300 N/A N/A
0.300 N/A N/A
-5 N/A 5
.95 1.2 1.45
measured by the oscilloscope.
H
Electrical Specifications
1
Unit Figure Notes
2
V 3
2
V 3
3, 4, 5
V 3, 4
4
V 3, 4
6
V 3
6
V 3
7
V 5
μA
8
pF
Datasheet