Phase Lock Loop (Pll) Power And Filter; Phase Lock Loop (Pll) Filter Requirements - Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Datasheet

2.4.1

Phase Lock Loop (PLL) Power and Filter

V and V
CCA
processor in the 775-land package. Since these PLLs are analog, they require low noise power
supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as
well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies
must be low pass filtered from V
The AC low-pass requirements, with input at V
•
< 0.2 dB gain in pass band
•
< 0.5 dB attenuation in pass band < 1 Hz
•
> 34 dB attenuation from 1 MHz to 66 MHz
•
> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in
.
Figure 2-1. Phase Lock Loop (PLL) Filter Requirements
–0.5 dB
–28 dB
–34 dB
NOTES:
1. Diagram not to scale.
2. No specification exists for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
Datasheet
are power sources required by the PLL clock generators for the Pentium 4
CCIOPLL
TT
0.2 dB
0 dB
Forbidden
Zone
DC 1 Hz
Passband
.
are as follows:
TT
Figure 2-1.
fpeak 1 MHz
Electrical Specifications
Forbidden
Zone
66 MHz fcore
High
Frequency
Band
Filter_Spec
19