Phase Lock Loop (Pll) Power And Filter; Phase Lock Loop (Pll) Filter Requirements; Datasheet - Intel SL8J6 - Pentium 4 Processor Datasheet

Electrical Specifications
2.3.1

Phase Lock Loop (PLL) Power and Filter

V and V
CCA
silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter.
Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings
(i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered
from V
CC
The AC low-pass requirements, with input at V
•
< 0.2 dB gain in pass band
•
< 0.5 dB attenuation in pass band < 1 Hz
•
> 34 dB attenuation from 1 MHz to 66 MHz
•
> 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in
refer to the appropriate platform design guide.
.
Figure 1. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
–0.5 dB
–28 dB
–34 dB
NOTES:
1. Diagram not to scale.
2. No specification exists for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
16
are power sources required by the PLL clock generators on the processor
CCIOPLL
.
0 dB
Forbidden
Zone
DC 1 Hz
Passband
are as follows:
CC
Figure 1. For recommendations on implementing the filter,
Forbidden
fpeak 1 MHz 66 MHz
Zone
fcore
High
Frequency
Band

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