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Configuration Tasks
SONET/SDH Configuration Tasks
clock source
Copyright © 2010, Juniper Networks, Inc.
Framing type, clock source, and the cable length for each controller
Framing type, line code, and clock source for each channel
Timeslot mapping and line speed for each fractional channel
HDLC channel information, such as data inversion information, CRC type, idle character,
MTU, and MRU
The following sections describe how to configure the layers on cOCx/STMx interfaces.
To configure SONET/SDH on a cOCx/STMx interface:
Select an interface.
1.
Specify a clock source for the interface.
2.
Specify that the mode be SDH, or accept the default mode, SONET.
3.
(Optional) Assign a text description or an alias to the interface.
4.
(Optional) Disable processing of SNMP link status information for the section and
5.
line layers of the interface.
Configure the path for the interface.
6.
(Optional—not recommended) Overwrite the automatic setting for the path signal
7.
label (C2) byte.
(Optional) Enable processing of SNMP link status information for the path layer of
8.
the interface.
(Optional) Configure the router to use remote defect indications (RDIs) at the path
9.
layer to determine the operational status of a path.
(MPLS fast reroute over SONET/SDH interfaces) Specify the time duration after
10.
which the router sets an alarm when it records a defect at the path layer.
(MPLS fast reroute over SONET/SDH interfaces) Specify the time duration after
11.
which the router sets an alarm when it records a defect at the line or section layer.
Configure APS/MSP for the interface.
12.
For information about configuring APS/MSP, see "Configuring APS/MSP" on page 87
in "Configuring Unchannelized OCx/STMx Interfaces" on page 71.
You must now configure the next layer on the interface: E1, T1, or E3. See "T1/E1
Configuration Tasks" on page 119 or "T3 Configuration Tasks" on page 126.
Use to configure the transmit clock source for the interface.
For production networks, configure all STMx ports on the line module for internal
chassis timing. You must also ensure that the chassis reference clock is of good quality
Chapter 4: Configuring Channelized OCx/STMx Interfaces
115
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