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AMD SR5650 Data Book

AMD SR5650 Data Book

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AMD SR5650 Databook
Technical Reference Manual
Rev 2.00
P/N: 47062_sr5650_ds_pub
© 2010 Advanced Micro Devices, Inc.

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  • Page 1 AMD SR5650 Databook Technical Reference Manual Rev 2.00 P/N: 47062_sr5650_ds_pub © 2010 Advanced Micro Devices, Inc.
  • Page 2 AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur.

  • Page 3: Table Of Contents

    Table of Contents Chapter 1: Overview 1.1 Introducing the SR5650 ..............................1-1 1.2 SR5650 Features .................................1-1 1.2.1 CPU Interface ...............................1-1 1.2.2 PCI Express® Interface ............................1-1 1.2.3 A-Link Express II Interface..........................1-1 1.2.4 Multiple Processor Support ..........................1-2 1.2.5 Multiple Northbridge Support ..........................1-2 1.2.6 Power Management Features ..........................1-2...
  • Page 4 Signals............................2-12 2.7 External Clock Chip ................................. 2-12 Chapter 3: Pin Descriptions and Strap Options 3.1 Pin Assignment Top View ..............................3-2 3.2 SR5650 Interface Block Diagram ............................3-4 3.3 CPU HyperTransport™ Interface ............................3-4 3.4 PCI Express® Interfaces ..............................3-5 3.4.1...
  • Page 5 7.3.1 Brief Description of an XOR Tree ........................7-1 7.3.2 Description of the XOR Tree for the SR5650 ......................7-2 7.3.3 XOR Tree Activation ............................7-2 7.3.4 XOR Tree for the SR5650............................7-3 7.4 VOH/VOL Test...................................7-4 7.4.1 Brief Description of a VOH/VOL Tree........................7-4 7.4.2 VOH/VOL Tree Activation..........................7-5...
  • Page 6 This page is left blank intentionally. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Table of Contents-4 Proprietary...
  • Page 7 List of Figures Figure 1-1: SR5650 Branding Diagram for A21 Production ASIC (Eutectic Part) ............... 1-3 Figure 1-2: SR5650 Branding Diagram for A21 Production ASIC (Lead Free Part) ..............1-3 Figure 2-1: SR5650 Internal Blocks and Interfaces ........................2-1 Figure 2-2: HyperTransport™ Interface Block Diagram .......................
  • Page 8 This page is left blank intentionally. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. List of Figures-2 Proprietary...
  • Page 9 Table 1-3: Acronyms and Abbreviations ............................1-4 Table 2-1: SR5650 HyperTransport™ Flow Control Buffers ......................2-3 Table 2-2: Types of Errors Detectable by the SR5650 AER Implementation ................2-10 Table 2-3: Types of HyperTransport™ Errors Supported by the SR5650 ..................2-11 Table 2-4: Possible Configurations for the PCI Express® General Purpose Links ..............2-12...
  • Page 10 This page intentionally left blank. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. List of Tables-2 Proprietary...

  • Page 11: Chapter 1: Overview

    A-Link Express II interface to AMD’s Southbridges such as the SP5100 (formerly SB700S). The SR5650 also comes equipped with the new HyperTransport™ 3 and PCIe Gen 2 technologies. All of these are achieved by a highly integrated, thermally efficient design in a 29mm x 29mm package.

  • Page 12: Multiple Processor Support

    1.2.8 Test Capability Features The SR5650 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per Million) ratio: • Full scan implementation on the digital core logic which provides about 97% fault coverage through ATPG (Automatic Test Pattern Generation Vectors).

  • Page 13: Device Id

    Device ID The SR5650 is a member of the AMD chipset family, which consists of different devices designed to support different platforms. Each device is identified by a device ID, which is stored in the NB_DEVICE_ID register. The device IDs for...

  • Page 14: Conventions And Notations

    Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a BIOS system or expansion card. BIST Built In Self Test. Dynamic Bus Inversion 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...
  • Page 15 Peripheral Component Interface ® ® PCIe PCI Express Phase Locked Loop POST Power On Self Test Pull-down Resistor Pull-up Resistor Reliability, Availability and Serviceability Southbridge To Be Added Voltage Regulation Module © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 16: Sr5650 Databook

    Conventions and Notations This page is left blank intentionally. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 17: Chapter 2: Functional Descriptions

    Chapter 2 Functional Descriptions This chapter describes the functional operation of the major interfaces of the SR5650 system logic chip. Figure 2-1 illustrates the SR5650 internal blocks and interfaces. HyperTransport™ 3 Unit Southbridge Root Expansion Complex Slots Expansion Slots Register Interface Figure 2-1 SR5650 Internal Blocks and Interfaces HyperTransport™...

  • Page 18: Figure 2-2 Hypertransport™ Interface Block Diagram

    The interface is illustrated below in Figure 2-3, “SR5650 HyperTransport™ Interface Signals.” The signal name and direction for each signal is shown with respect to the SR5650. Detailed descriptions of the signals are given in Section 3.3, “CPU HyperTransport™ Interface‚’ on page 3-4.

  • Page 19: Hypertransport™ Flow Control Buffers

    Full HyperTransport-defined BIST support for both internal and external loopback modes 2.1.2 HyperTransport™ Flow Control Buffers The SR5650 HTIU implements the following flow control buffers in its receiver: Table 2-1 SR5650 HyperTransport™ Flow Control Buffers Flow Control Buffer Type Posted...

  • Page 20: Iommu

    On-chip caching is provided in order to speed up translation and reduce or eliminate the number of system memory accesses required. Every PCIe core contains a local translation cache, and the SR5650 also contains a shared global translation cache.

  • Page 21: Integrated Ioapic Support

    MSI Interrupt Handling and MSI to HT Interrupt Conversion In MSI interrupt mode, all interrupts are sent directly from the endpoint devices through the SR5650 up to the processor complex. All MSI interrupts are converted into HT-formatted interrupts. For MSIs from PCI Express endpoint devices and internally generated PCI Express interrupts, the conversion occurs in the associated IOMMU L1 block.

  • Page 22: Figure 2-4 Interrupt Routing Paths In Legacy Mode

    SR5650 SR5650 Endpoint Device Device INTx Message from device attached to primary SR5650 INTx Message from device attached to secondary SR5650 Interrupts from SB IOAPIC Figure 2-4 Interrupt Routing Paths in Legacy Mode 2.4.7.2 Legacy Mode with Integrated IOAPIC For both the primary and secondary SR5650s, legacy INTx messages are routed to the integrated IOAPICs of the SR5650s, which generates interrupt requests.

  • Page 23: Ras Features

    Parity Protection 2.5.1 All memories in SR5650 are parity protected to reduce the possibility of silent data corruption. Multiple parity words are interleaved to convert burst errors (multiple physically adjacent bits corrupted) into multiple single-bit detectable errors to increase robustness. The minimum number of interleaved parity words in any on-board memory is 4. All macros contain test circuitry for software to generate false errors on either the read or write side of the memory for verification of error handling routines.

  • Page 24: Nmi# And Syncfloodin

    NMI# and SYNCFLOODIN# The SR5650 may configure the DFT_GPIO0/NMI# pin as an input pin for triggering an upstream NMI packet to the processor complex. The pin should be driven by a BMC. An internal sticky status bit records the use of the NMI# pin.

  • Page 25: Error Reporting And Logging

    Figure 2-7 Suggested Platform Level RAS Sideband Signal Connections 2.5.5 Error Reporting and Logging 2.5.5.1 PCI Error Logging The SR5650 implements all PCI standard error logging bits for all on-board devices and functions including the host bridge device, IOMMU, and PCI Express bridges. ® 2.5.5.2 PCIe Advanced Error Reporting ®...

  • Page 26: Table 2-2 Types Of Errors Detectable By The Sr5650 Aer Implementation

    For upstream completions, error status is propagated up to the processor and AER information may be logged. Table 2-2 lists the types of errors that are detectable by the SR5650 AER implementation. For details, see the PCI Express 2.0 Base Specification.

  • Page 27: Interrupt Generation On Errors

    Link Disable State The SR5650 has the ability to put PCIe links into the disabled state as an error response in order to help stop data movement within the system. Links which received fatal errors may be disabled. Also, a HyperTransport syncflood event may be used to trigger all links to enter the disabled state.

  • Page 28: Ht Syncflood Based On Pcie® Error

    Error The SR5650 has the ability to put the HyperTransport link into the syncflood state when a fatal or non-fatal error is received on the PCIe interface. This is done in order to help stop data movement within the system.

  • Page 29: Table 3-2: Pci Express® Interface For General Purpose External Devices

    Chapter 3 Pin Descriptions and Strap Options This chapter gives the pin descriptions and the strap options for the SR5650. To jump to a topic of interest, use the following list of hyperlinked cross references: “Pin Assignment Top View” on page 3-2 “SR5650 Interface Block Diagram”...

  • Page 30: Pin Assignment Top View

    PCIe GPP3 General Purpose Interface Power Management Interface Core Power PCIe Main I/O Power PCIe 1.8V I/O Power and PLL Power GPIO 1.8V I/O Power HyperTransport™ Interface Power Grounds Other 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...
  • Page 31 PCIe GPP3 General Purpose Interface Power Management Interface Core Power PCIe Main I/O Power PCIe 1.8V I/O Power and PLL Power GPIO 1.8V I/O Power HyperTransport Interface Power Grounds Other © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 32: Sr5650 Interface Block Diagram

    SR5650 Interface Block Diagram SR5650 Interface Block Diagram Figure 3-1 shows the different interfaces on the SR5650. Interface names in blue are hyperlinks to the corresponding sections in this chapter. HT_RXCAD[15:0]P, HT_RXCAD[15:0]N HT_RXCLK[1:0]P, HT_RXCLK[1:0]N HT_RXCTL[1:0]P, HT_RXCTL[1:0]N ® PCIe Interface HyperTransport™...

  • Page 33: Pci Express Interfaces

    Receive Data Differential Pairs on the SB_TX[3:0]N complements Southbridge. Southbridge Receive Data Differential Pairs. Connect to the SB_RX[3:0]P, 50 between VDDA18PCIE VSSA_PCIE corresponding Transmit Data Differential Pairs on the SB_RX[3:0]N complements Southbridge. © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 34: Clock Interface

    HyperTransport link should be disconnected and go into a low-power state. It is a single-ended signal. Input from the motherboard signifying that the power to the SR5650 is up and ready. Signal High means all power planes are valid. It is not observed internally...

  • Page 35: Miscellaneous Pins

    C interface data signal for external EEPROM based strap loading. STRP_DATA VDD18 – See the SR5650 Strap Document for details on the operation. When High, puts the SR5650 in test mode and disables the TESTMODE VDD18 – SR5650 from operating normally.
  • Page 36 U21, V22, W21, Y22 C24, C25, C26, C27, C28, VDDHTTX 1.2V D22, D23, E22, F22, G22, HyperTransport Transmit Interface I/O power VDDA18HTPLL 1.8V HyperTransport interface 1.8V PLL Power Total Power Pin Count 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 37: Ground Pins

    U11, U12, U13, U15, U17, U18, U22, U25, U28, U4, U7, V12, V13, V14, V15, V16, V17, V21, V23, V26, V3, V6, W1, W22, W25, W28, W4, W7, Y23, Y26, Y3, Y6, Y8 © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 38: Strapping Options

    Strapping Options 3.10 Strapping Options The SR5650 provides strapping options to define specific operating parameters. The strap values are latched into internal registers after the assertion of the POWERGOOD signal to the SR5650. Table 3-10, “Strap Definitions for the SR5650,”...

  • Page 39: Chapter 4: Timing Specifications

    Chapter 4 Timing Specifications HyperTransport™ Bus Timing For HyperTransport™ bus timing information, please refer to specifications by AMD. ® PCI Express Differential Clock AC Specifications ® Table 4-1 Timing Requirements for PCIe Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz) Symbol...

  • Page 40: Oscin Reference Clock Timing Parameters

    Duty Cycle Notes: More details are available in AMD HyperTransport 3.0 Reference Clock Specification and AMD Family 10h Processor Reference Clock Parameters, document # 34864 1 Single-ended measurement at crossing point. Value is maximum-minimum over all time. DC Value of common mode is not important due to blocking cap.

  • Page 41: Power Up

    Power Rail Sequence Table 4-4 Power Rail Groupings for the SR5650 ACPI Group Name Power rail name Voltage Description STATE 1.8V VDD18 1.8V S0-S2 I/O power for GPIO pads VDDA18PCIE 1.8V S0-S2 PCI Express interface 1.8V IO and PLL power VDDA18HTPLL 1.8V...

  • Page 42: Power Down

    For power down, the rails should either be turned off simultaneously or in the reversed order of the power up sequence. Variations in speeds of decay due to different capacitor discharge rates can be safely ignored. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 43: Chapter 5: Electrical Characteristics And Physical Data

    Differential Input High Voltage +150 Absolute Crossing Point Voltage +250 +550 CROSS Variation of V over all rising +140 CROSS DELTA CROSS clock edges Ring-back Voltage Margin -100 +100 © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 44: Sr5650 Thermal Characteristics

    3 - The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device. The maximum ambient temperature is dependent on the heat sink design, and the value given here is based on AMD’s reference heat sink solution for the SR5650.

  • Page 45: Thermal Diode Characteristics

    5.2.2 Thermal Diode Characteristics The SR5650 has an on-die thermal diode, with its positive and negative terminals connected to the THERMALDIODE_P and THERMALDIODE_N pins respectively. Combined with a thermal sensor circuit, the diode temperature, and hence the ASIC junction temperature, can be derived from a differential voltage reading (V). The equation relating the temperature to V is given below.

  • Page 46: Package Information

    Package Information Package Information Figure 5-2 Table 5-6 describe the physical dimensions of the SR5650 package. Figure 5-3 shows the detailed ball arrangement for the SR5650. MOD-00094-03 Figure 5-2 SR5650 692-Pin FCBGA Package Outline Table 5-6 SR5650 692-Pin FCBGA Package Physical Dimensions Ref.

  • Page 47: Pressure Specification

    Package Information Table 5-6 SR5650 692-Pin FCBGA Package Physical Dimensions Ref. Min. (mm) Typical (mm) Max. (mm) 0.20 Note: Maximum height of SMT components is 0.650 mm. Figure 5-3 SR5650 Ball Arrangement (Bottom View) 5.3.1 Pressure Specification To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below: •...

  • Page 48: Board Solder Reflow Process Recommendations

    Typical 60 – 80 seconds Ramp Rate Ramp up and Cooling <2C / second Peak Max. 245C 235C +/-5C Temperature at peak 240C to 245C 10 – 30 seconds within 5C 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 49: Figure 5-4 Rohs/Lead-Free Solder (Sac305/405 Tin-Silver-Copper) Reflow Profile

    45 - 90 sec. Max. 60 – 80 sec. typical 60 - 80 sec. typical Pre-heating Zone 2 min to 4 min Max. Heating Time Figure 5-4 RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...
  • Page 50 Package Information This page is left blank intentionally. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 51: Chapter 6: Power Management And Acpi

    This chapter describes the support for ACPI power management provided by the SR5650. The SR5650 system controller supports ACPI Revision 2.0. The hardware, system BIOS, and drivers of the SR5650 have the logic required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and Device Requirements version 2.1.

  • Page 52: Advanced Micro Devices, Inc

    ACPI Power Management Implementation This page intentionally left blank. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 53: Chapter 7: Testability

    Test Capability Features The SR5650 system controller has integrated test modes and capabilities. These test features cover both the ASIC and board level testing. The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part.

  • Page 54: Description Of The Xor Tree For The Sr5650

    Output Pin A number 7.3.2 Description of the XOR Tree for the SR5650 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Section 7.3.4...

  • Page 55: Xor Tree For The Sr5650

    XOR Tree 7.3.4 XOR Tree for the SR5650 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Table 7-3 for the list of the signals included on the XOR tree.

  • Page 56: Voh/Vol Test

    The VOH/VOL logic provides signal output on I/O’s when test patterns are applied to the TEST_ODD and TEST_EVEN pins. A sample of a generic VOH/VOL tree is shown in the figure below. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc.

  • Page 57: Voh/Vol Tree Activation

    7. Load JTAG instruction register with the instruction 0010 0000. 8. Load JTAG instruction register with the instruction 0101 1101. 9. Go to Run-Test_Idle state. 10. Set POWERGOOD to 1. © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...

  • Page 58: Voh/Vol Pin List

    VOH/VOL pin list Table 7-5 below shows the SR5650 VOH/VOL Tree. There is no specific order of connection. Under the Control column, an “Odd” or “Even” indicates that the logical output of the pin is same as the input to the “TEST_ODD” or the “TEST_EVEN”...
  • Page 59 NC/NC AH10/AG10 PWM_GPIO1 Even PWM_GPIO2 PWM_GPIO5 Even PCIE_RESET_GPIO1 PCIE_RESET_GPIO4 Even PCIE_RESET_GPIO5 DFT_GPIO0 Even DFT_GPIO1 DFT_GPIO2 Even DFT_GPIO3 DFT_GPIO4 Even DFT_GPIO5 DBG_GPIO0 Even DBG_GPIO1 DBG_GPIO2 Even DBG_GPIO3 ALLOW_LDTSTOP Even LDTSTOP# © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary...
  • Page 60 VOH/VOL Test This page intentionally left blank. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Proprietary...

  • Page 61: Appendix A Pin Listings

    Appendix A Pin Listings This appendix contains pin listings for the SR5650 sorted in different ways. To go to the listing of interest, use the linked cross-references below: “SR5650 Pin Listing Sorted by Ball Reference” on page A-2 “SR5650 Pin Listing Sorted by Pin Name” on page A-9 ©...

  • Page 62: Sr5650 Pin Listing Sorted By Ball Reference

    SR5650 Pin Listing Sorted by Ball Reference SR5650 Pin Listing Sorted by Ball Reference Table A-1 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name AA18 VDDPCIE AB23 GPP1_TX1P AA19...
  • Page 63 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name AE11 AE12 AF20 AE13 AF21 SB_TX2P VDDPCIE AE14 AF22 AE15 AF23 SB_TX1P AE16 GPP3_RX4P AF24 AE17 AF25 SB_RX1P AE18 GPP3_RX2P AF26...
  • Page 64 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name PWM_GPIO6 OSCIN VDDHTTX VDD18 VDDHTTX PCIE_RESET_GPIO1 VDDHTTX VDDPCIE VDDHTTX I2C_CLK VDDHTTX AH10 DBG_GPIO2 VDDPCIE AH11 DBG_GPIO1 AH12 DFT_GPIO4 GPP1_RX6N AH13 DFT_GPIO2...
  • Page 65 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name VDDA18PCIE GPP1_TX9N GPP1_RX5P VDDA18PCIE PCE_TCALRP VDDA18HTPLL GPP1_RX3P VDDHTTX PWM_GPIO3 HT_TXCAD10P HT_TXCAD10N GPP1_RX1N GPP1_RX0P HT_TXCAD2P VDDA18PCIE GPP1_TX8P HT_TXCAD2N VDDA18PCIE PCE_TCALRN GPP1_TX9P LDTSTOP#...
  • Page 66 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name HT_TXCAD3P GPP1_RX12N HT_TXCAD3N GPP1_RX12P GPP1_TX14P GPP1_RX10N VDDPCIE GPP1_RX10P VDDHT VDDPCIE VDDA18PCIE HT_TXCAD14P GPP1_REFCLKN HT_TXCAD14N VDDPCIE VDDC HT_TXCAD6P GPP1_TX11N HT_TXCAD6N HT_REFCLKN VDDC...
  • Page 67 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name GPP1_RX15N GPP1_RX15P VDDHT VDDPCIE VDDPCIE HT_RXCTL1N HT_RXCTL1P VDDC HT_RXCTL0N HT_RXCTL0P VDDC VDDC VDDC VDDC VDDHT VDDHT VDDPCIE HT_RXCAD14N HT_TXCTL1P HT_RXCAD14P HT_TXCTL1N...
  • Page 68 SR5650 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name VDDHT VDDA18PCIE HT_RXCLK1N HT_RXCLK1P VDDHT HT_RXCLK0N HT_RXCAD13N HT_RXCLK0P HT_RXCAD13P HT_RXCAD5N HT_RXCAD5P VDDPCIE VDDPCIE VDDHT HT_RXCAD12N HT_RXCAD12P HT_RXCAD4N HT_RXCAD4P VDDPCIE THERMALDIODE_P 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc.

  • Page 69: Sr5650 Pin Listing Sorted By Pin Name

    SR5650 Pin Listing Sorted by Ball Reference SR5650 Pin Listing Sorted by Pin Name Ball Name Ball # Ball Name Ball # Ball Name Ball # GPP1_RX4N GPP1_TX5P ALLOW_LDTSTOP GPP1_RX4P GPP1_TX6N DBG_GPIO0/SERR_F ATAL# GPP1_RX5N GPP1_TX6P DBG_GPIO1 GPP1_RX5P GPP1_TX7N DBG_GPIO2 GPP1_RX6N...
  • Page 70 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # HT_REFCLKN HT_RXCLK0N HT_TXCAD8N HT_REFCLKP HT_RXCLK0P HT_TXCAD8P HT_RXCAD0N AD27 HT_RXCLK1N HT_TXCAD9N HT_RXCAD0P AD28 HT_RXCLK1P HT_TXCAD9P HT_RXCAD10N AB24 HT_RXCTL0N HT_TXCALN HT_RXCAD10P AB25 HT_RXCTL0P...
  • Page 71 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # PCIE_RESET_GPIO3 PCIE_RESET_GPIO4 PCIE_RESET_GPIO5 POWERGOOD PWM_GPIO1 AE12 PWM_GPIO2 AE14 PWM_GPIO3 PWM_GPIO4 PWM_GPIO5 PWM_GPIO6 SB_RX0N AH26 SB_RX0P AG26 AF11 SB_RX1N AG25 AF13 SB_RX1P...
  • Page 72 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # VDDA18HTPLL VDDC VDDPCIE VDDA18PCIE VDDC VDDPCIE AA10 VDDA18PCIE VDDC VDDPCIE AA12 VDDA18PCIE VDDC VDDPCIE AA16 VDDA18PCIE VDDHT AA22 VDDPCIE AA18 VDDA18PCIE...
  • Page 73 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # VDDPCIE AF28 VDDPCIE VDDPCIE AC10 VDDPCIE AC12 AC14 AG27 AC16 AC18 AH11 AC20 AH13 AC25 AH15 AC28 AH17 AH19 AH21 AH23...
  • Page 74 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Appendix A-14 Proprietary...
  • Page 75 SR5650 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary Appendix A-15...
  • Page 76 SR5650 Pin Listing Sorted by Ball Reference This page is left blank intentionally. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Appendix A-16 Proprietary...

  • Page 77: Appendix B Revision History

    Appendix B Revision History Rev. 2.00 (Dec 2010) • First release of the public version. © 2010 Advanced Micro Devices, Inc. 47062 SR5650 Databook 2.00 Proprietary Appendix B-1...
  • Page 78 This page intentionally left blank. 47062 SR5650 Databook 2.00 © 2010 Advanced Micro Devices, Inc. Appendix B-2 Proprietary...

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