Page 2
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur.
Table of Contents Chapter 1: Overview 1.1 Introducing the SR5650 ..............................1-1 1.2 SR5650 Features .................................1-1 1.2.1 CPU Interface ...............................1-1 1.2.2 PCI Express® Interface ............................1-1 1.2.3 A-Link Express II Interface..........................1-1 1.2.4 Multiple Processor Support ..........................1-2 1.2.5 Multiple Northbridge Support ..........................1-2 1.2.6 Power Management Features ..........................1-2...
Page 5
7.3.1 Brief Description of an XOR Tree ........................7-1 7.3.2 Description of the XOR Tree for the SR5650 ......................7-2 7.3.3 XOR Tree Activation ............................7-2 7.3.4 XOR Tree for the SR5650............................7-3 7.4 VOH/VOL Test...................................7-4 7.4.1 Brief Description of a VOH/VOL Tree........................7-4 7.4.2 VOH/VOL Tree Activation..........................7-5...
Page 9
Table 1-3: Acronyms and Abbreviations ............................1-4 Table 2-1: SR5650 HyperTransport™ Flow Control Buffers ......................2-3 Table 2-2: Types of Errors Detectable by the SR5650 AER Implementation ................2-10 Table 2-3: Types of HyperTransport™ Errors Supported by the SR5650 ..................2-11 Table 2-4: Possible Configurations for the PCI Express® General Purpose Links ..............2-12...
A-Link Express II interface to AMD’s Southbridges such as the SP5100 (formerly SB700S). The SR5650 also comes equipped with the new HyperTransport™ 3 and PCIe Gen 2 technologies. All of these are achieved by a highly integrated, thermally efficient design in a 29mm x 29mm package.
1.2.8 Test Capability Features The SR5650 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per Million) ratio: • Full scan implementation on the digital core logic which provides about 97% fault coverage through ATPG (Automatic Test Pattern Generation Vectors).
Device ID The SR5650 is a member of the AMD chipset family, which consists of different devices designed to support different platforms. Each device is identified by a device ID, which is stored in the NB_DEVICE_ID register. The device IDs for...
Chapter 2 Functional Descriptions This chapter describes the functional operation of the major interfaces of the SR5650 system logic chip. Figure 2-1 illustrates the SR5650 internal blocks and interfaces. HyperTransport™ 3 Unit Southbridge Root Expansion Complex Slots Expansion Slots Register Interface Figure 2-1 SR5650 Internal Blocks and Interfaces HyperTransport™...
The interface is illustrated below in Figure 2-3, “SR5650 HyperTransport™ Interface Signals.” The signal name and direction for each signal is shown with respect to the SR5650. Detailed descriptions of the signals are given in Section 3.3, “CPU HyperTransport™ Interface‚’ on page 3-4.
Full HyperTransport-defined BIST support for both internal and external loopback modes 2.1.2 HyperTransport™ Flow Control Buffers The SR5650 HTIU implements the following flow control buffers in its receiver: Table 2-1 SR5650 HyperTransport™ Flow Control Buffers Flow Control Buffer Type Posted...
On-chip caching is provided in order to speed up translation and reduce or eliminate the number of system memory accesses required. Every PCIe core contains a local translation cache, and the SR5650 also contains a shared global translation cache.
MSI Interrupt Handling and MSI to HT Interrupt Conversion In MSI interrupt mode, all interrupts are sent directly from the endpoint devices through the SR5650 up to the processor complex. All MSI interrupts are converted into HT-formatted interrupts. For MSIs from PCI Express endpoint devices and internally generated PCI Express interrupts, the conversion occurs in the associated IOMMU L1 block.
SR5650 SR5650 Endpoint Device Device INTx Message from device attached to primary SR5650 INTx Message from device attached to secondary SR5650 Interrupts from SB IOAPIC Figure 2-4 Interrupt Routing Paths in Legacy Mode 2.4.7.2 Legacy Mode with Integrated IOAPIC For both the primary and secondary SR5650s, legacy INTx messages are routed to the integrated IOAPICs of the SR5650s, which generates interrupt requests.
Parity Protection 2.5.1 All memories in SR5650 are parity protected to reduce the possibility of silent data corruption. Multiple parity words are interleaved to convert burst errors (multiple physically adjacent bits corrupted) into multiple single-bit detectable errors to increase robustness. The minimum number of interleaved parity words in any on-board memory is 4. All macros contain test circuitry for software to generate false errors on either the read or write side of the memory for verification of error handling routines.
NMI# and SYNCFLOODIN# The SR5650 may configure the DFT_GPIO0/NMI# pin as an input pin for triggering an upstream NMI packet to the processor complex. The pin should be driven by a BMC. An internal sticky status bit records the use of the NMI# pin.
Figure 2-7 Suggested Platform Level RAS Sideband Signal Connections 2.5.5 Error Reporting and Logging 2.5.5.1 PCI Error Logging The SR5650 implements all PCI standard error logging bits for all on-board devices and functions including the host bridge device, IOMMU, and PCI Express bridges. ® 2.5.5.2 PCIe Advanced Error Reporting ®...
For upstream completions, error status is propagated up to the processor and AER information may be logged. Table 2-2 lists the types of errors that are detectable by the SR5650 AER implementation. For details, see the PCI Express 2.0 Base Specification.
Link Disable State The SR5650 has the ability to put PCIe links into the disabled state as an error response in order to help stop data movement within the system. Links which received fatal errors may be disabled. Also, a HyperTransport syncflood event may be used to trigger all links to enter the disabled state.
Error The SR5650 has the ability to put the HyperTransport link into the syncflood state when a fatal or non-fatal error is received on the PCIe interface. This is done in order to help stop data movement within the system.
Chapter 3 Pin Descriptions and Strap Options This chapter gives the pin descriptions and the strap options for the SR5650. To jump to a topic of interest, use the following list of hyperlinked cross references: “Pin Assignment Top View” on page 3-2 “SR5650 Interface Block Diagram”...
SR5650 Interface Block Diagram SR5650 Interface Block Diagram Figure 3-1 shows the different interfaces on the SR5650. Interface names in blue are hyperlinks to the corresponding sections in this chapter. HT_RXCAD[15:0]P, HT_RXCAD[15:0]N HT_RXCLK[1:0]P, HT_RXCLK[1:0]N HT_RXCTL[1:0]P, HT_RXCTL[1:0]N ® PCIe Interface HyperTransport™...
HyperTransport link should be disconnected and go into a low-power state. It is a single-ended signal. Input from the motherboard signifying that the power to the SR5650 is up and ready. Signal High means all power planes are valid. It is not observed internally...
C interface data signal for external EEPROM based strap loading. STRP_DATA VDD18 – See the SR5650 Strap Document for details on the operation. When High, puts the SR5650 in test mode and disables the TESTMODE VDD18 – SR5650 from operating normally.
Strapping Options 3.10 Strapping Options The SR5650 provides strapping options to define specific operating parameters. The strap values are latched into internal registers after the assertion of the POWERGOOD signal to the SR5650. Table 3-10, “Strap Definitions for the SR5650,”...
Chapter 4 Timing Specifications HyperTransport™ Bus Timing For HyperTransport™ bus timing information, please refer to specifications by AMD. ® PCI Express Differential Clock AC Specifications ® Table 4-1 Timing Requirements for PCIe Differential Clocks (GPP1_REFCLK and GPP3_REFCLK at 100MHz) Symbol...
Duty Cycle Notes: More details are available in AMD HyperTransport 3.0 Reference Clock Specification and AMD Family 10h Processor Reference Clock Parameters, document # 34864 1 Single-ended measurement at crossing point. Value is maximum-minimum over all time. DC Value of common mode is not important due to blocking cap.
Power Rail Sequence Table 4-4 Power Rail Groupings for the SR5650 ACPI Group Name Power rail name Voltage Description STATE 1.8V VDD18 1.8V S0-S2 I/O power for GPIO pads VDDA18PCIE 1.8V S0-S2 PCI Express interface 1.8V IO and PLL power VDDA18HTPLL 1.8V...
3 - The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device. The maximum ambient temperature is dependent on the heat sink design, and the value given here is based on AMD’s reference heat sink solution for the SR5650.
5.2.2 Thermal Diode Characteristics The SR5650 has an on-die thermal diode, with its positive and negative terminals connected to the THERMALDIODE_P and THERMALDIODE_N pins respectively. Combined with a thermal sensor circuit, the diode temperature, and hence the ASIC junction temperature, can be derived from a differential voltage reading (V). The equation relating the temperature to V is given below.
Package Information Table 5-6 SR5650 692-Pin FCBGA Package Physical Dimensions Ref. Min. (mm) Typical (mm) Max. (mm) 0.20 Note: Maximum height of SMT components is 0.650 mm. Figure 5-3 SR5650 Ball Arrangement (Bottom View) 5.3.1 Pressure Specification To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below: •...
This chapter describes the support for ACPI power management provided by the SR5650. The SR5650 system controller supports ACPI Revision 2.0. The hardware, system BIOS, and drivers of the SR5650 have the logic required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and Device Requirements version 2.1.
Test Capability Features The SR5650 system controller has integrated test modes and capabilities. These test features cover both the ASIC and board level testing. The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part.
Output Pin A number 7.3.2 Description of the XOR Tree for the SR5650 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Section 7.3.4...
XOR Tree 7.3.4 XOR Tree for the SR5650 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Table 7-3 for the list of the signals included on the XOR tree.
VOH/VOL pin list Table 7-5 below shows the SR5650 VOH/VOL Tree. There is no specific order of connection. Under the Control column, an “Odd” or “Even” indicates that the logical output of the pin is same as the input to the “TEST_ODD” or the “TEST_EVEN”...
Need help?
Do you have a question about the SR5650 and is the answer not in the manual?
Questions and answers