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18.3.3 I
2
C Bus Control Register (IICC)
IICC is an 8-bit register composed of bits which control the SO latch status.
IICC is read or written with 8-bit manipulation instructions and bit manipulation instructions. When a read is performed,
IICC is read as "00". The format of the IICC register is shown in Figure 18-4. The IICC register must not be written to during
a transmit, receive, or transmit/receive operation.
RESET input clears SBIC to 00H.
7
6
IICC
0
0
18.4 3-WIRE SERIAL I/O MODE
The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface.
Basically, communication is performed using three lines: the serial clock (SCK0), serial data output (SO0), and serial
data input (SI0). Generally, a handshake line is necessary for checking the communication status.
Figure 18-5 Example of 3-Wire Serial I/O System Configuration
3-wire serial I/O ↔
↔ ↔
↔ ↔ 3-wire serial I/O
Note Handshaking lines
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE
Figure 18-4 Format of I
5
4
3
2
0
0
0
0
STT
Master CPU
SCK
SO
SI
Port (Interrupt)
Port
User's Manual U11316EJ4V1UD
2
C Bus Control Register (IICC)
1
0
Address
After reset
SPT
0FF80H
00H
SPT
0
Not affected
1
Sets SO latch (1)
STT
0
Not affected
1
Clears SO latch (0)
Slave CPU
SCK
SI
SO
Note
Port
Interrupt (Port)
R/W
R/W
Operation
Operation
451
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