Table of Contents
Advertisement
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
(1) 5-bit counter
Counter that counts the clock (f
with the frequency selected by the low-order 4 bits of the baud rate generator control registers (BRGC/BRGC2).
(2) Frequency divider
Scales the internal clock (f
input (ASCK/ASCK2), and selects fPRS with the next-stage selector.
(3) Both-edge detection circuit
Detects both edges of the ASCK/ASCK2 pin input signal and generates a signal with a frequency twice that of the ASCK/
ASCK2 input clock.
17.4.2 Baud Rate Generator Control Register (BRGC, BRGC2)
The BRGC and BRGC2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift
clock in 3-wire serial I/O mode.
These registers can be read/written with an 8-bit manipulation instruction. The BRGC and BRGC2 format is shown in
Figure 17-15.
RESET input clears the BRGC register to 00H.
Caution When a baud rate generator control register (BRGC, BRGC2) write instruction is executed, the 5-bit
counter and 1/2 frequency divider operations are reset. Consequently, if a write to the BRGC and
BRGC2 is performed during communication, the generated baud rate clock may be disrupted,
preventing normal communication from continuing. The BRGC and BRGC2 should therefore not be
written to during communication.
) by which the output from the frequency divider is selected. Generates a signal
PRS
/2) or, in asynchronous serial interface mode, a clock that is twice the external baud rate
XX
User's Manual U11316EJ4V1UD
437
Advertisement
Table of Contents
