Timer/Counter 0 Control Registers - NEC uPD784038 Series User Manual

8.3 TIMER/COUNTER 0 CONTROL REGISTERS

(1) Timer control register 0 (TMC0)
The timer/counter 0 TM0 count operation is controlled by the low-order 4 bits in the TMC0 (the high-order 4 bits control the
count operation of the TM3/TM3W of the timer 3).
TMC0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of the TMC0
is shown in Figure 8-2.
RESET input clears TMC0 to 00H.
7 6
TMC0 CE3 0
Remark The OVF0 bit is reset by software only.
CHAPTER 8 TIMER/COUNTER 0
Figure 8-2 Timer Control Register 0 (TMC0) Format
5 4 3 2
0 BW3 CE0 OVF0
User's Manual U11316EJ4V1UD
1 0 Address After Reset
0 0 0FF5DH 00H
OVF0
0
No overflow
1 Overflow (count up from FFFFH to 0000H)
CE0 TM0 Count Operation Control
Count operation stopped with count
0
cleared
Count operation enabled
1
Controls count operation of the TM3/TM3W of the
timer 3 (see Figure 11-2).
R/W
R/W
TM0 Overflow Flag
193