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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
17.3.4 Operation When Transmission Only is Enabled
A transmit operation is performed when the CTXEn bit of clocked serial interface mode register (CSIMn) is set (to 1).
The transmit operation starts when a write to the shift register (SIOn) is performed while the CTXEn bit is set (to 1).
When the CTXEn bit is cleared (to 0), the SOn pin is in the output high level.
(1) When the internal clock is selected as the serial clock
When transmission starts, the serial clock is output from the SCKn pin and data is output in sequence from SIOn to
the SOn pin in synchronization with the fall of the serial clock, and SIn pin signals are shifted into SIOn in synchronization
with the rise of the serial clock.
There is a delay of up to one SCKn clock cycle between the start of transmission and the first fall of SCKn.
If transmission is disabled during the transmit operation (by clearing (to 0) the CTXEn bit), SCKn clock output is stopped
and the transmit operation is discontinued on the next rise of SCKn. In this case an interrupt request (INTCSIn) is
not generated, and the SOn pin becomes output high level.
(2) When an external clock is selected as the serial clock
When transmission starts, data is output in sequence from SIOn to the SOn pin in synchronization with the fall of the
serial clock input to the SCKn pin after the start of transmission, and SIn pin signals are shifted into SIOn in
synchronization with the rise of the SCKn pin input. If transmission has not started, shift operations are not performed
and the SOn pin output level does not change even if the serial clock is input to the SCKn pin.
If transmission is disabled during the transmit operation (by clearing (to 0) the CTXEn bit), the transmit operation is
discontinued and subsequent SCKn input is ignored. In this case an interrupt request (INTCSIn) is not generated, and
the SOn pin becomes output high level.
Remark n = 1 or 2
17.3.5 Operation When Reception Only is Enabled
A receive operation is performed when the CRXEn bit of the clocked serial interface mode register (CSIMn) is set (to
1). The receive operation starts when the CRXEn changes from "0" to "1", or when a read from shift register (SIOn) is
performed.
(1) When the internal clock is selected as the serial clock
When reception starts, the serial clock is output from the SCKn pin and the SIn pin data is fetched in sequence into
shift register (SIOn) in synchronization with the rise of the serial clock.
There is a delay of up to one SCKn clock cycle between the start of reception and the first fall of SCKn.
If reception is disabled during the receive operation (by clearing (to 0) the CRXEn bit), SCKn clock output is stopped
and the receive operation is discontinued on the next rise of SCKn. In this case an interrupt request (INTCSIn) is not
generated, and the contents of the SIOn are undefined.
(2) When an external clock is selected as the serial clock
When reception starts, the SIn pin data is fetched into shift register (SIOn) in synchronization with the rise of the serial
clock input to the SCKn pin after the start of reception. If reception has not started, shift operations are not performed
even if the serial clock is input to the SCKn pin.
If reception is disabled during the receive operation (by clearing (to 0) the CRXEn bit), the receive operation is
discontinued and subsequent SCKn input is ignored. In this case an interrupt request (INTCSIn) is not generated.
Remark n = 1 or 2
User's Manual U11316EJ4V1UD
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