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CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
17.3.3 Basic Operation Timing
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit
by bit in MSB-first or LSB-first order in synchronization with the serial clock.
MSB/LSB switching is specified by the DIRn bit of the clock serial interface mode register (CSIMn).
Transmit data is output in synchronization with the fall of SCKn, and receive data is sampled on the rise of SCKn.
An interrupt request (INTCSIn) is generated on the 8th rise of SCKn.
When the internal clock is used as SCKn, SCKn output is stopped on the 8th rise of SCKn and SCKn remains high until
the next data transmit or receive operation is started.
3-wire serial I/O mode timing is shown in Figure 17-12.
(a) MSB-first
Note
SCKn
SIn (Input)
SOn (Output)
INTCSIn
Remark n = 1 or 2
Figure 17-12 3-Wire Serial I/O Mode Timing (1/2)
1
2
3
4
5
DI7
DI6
DI5
DI4
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Start of transfer synchronized with fall of SCKn
Execution of instruction that writes to SIOn
User's Manual U11316EJ4V1UD
6
7
8
DI3
DI2
DI1
DI0
Transfer End
Interrupt Generation
Note Master CPU: Output
Slave CPU:
Input
431
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