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4.4 CAUTIONS
The following cautions apply to the clock generator.
4.4.1 When an External Clock is Input
(1) If the STOP mode is used with external clock input, the EXTC bit of the oscillation stabilization time specification register
(OSTS) must be set (to 1). If the STOP mode is used when the EXTC bit is in the cleared (to 0) state, the µ PD784038 may
be damaged or suffer reduced reliability.
(2) When setting the EXTC bit of the OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the X1
pin, to the X2 pin.
(3) Even when inputting the external clock by clearing the EXTC bit of the oscillation stabilization time specification register
(OSTS) to 0, input a signal in phase reverse to that of the signal input to the X1 pin, to the X2 pin, whenever possible.
Otherwise, more malfunctioning may occur due to noise.
(4) When an external clock is input, this should be performed with a HCMOS device, or a device with the equivalent drive
capability.
(5) A signal should not be extracted from the X1 and X2 pins. If a signal is extracted, it should be extracted from point a in Figure
4-5.
(6) The wiring connecting the X1 pin to the X2 pin via an inverter, in particular, should be made as short as possible.
CHAPTER 4 CLOCK GENERATOR
Figure 4-5 Signal Extraction with External Clock Input
a
User's Manual U11316EJ4V1UD
µ PD784038
X1
X2
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