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The µ PD784038 incorporates two 12-bit resolution PWM (pulse width modulation) output circuit channels. The active
level of the PWM output pulses can be selected as high or low. The PWM output ports have a dual function as pins P10
and P11.
13.1 PWM OUTPUT UNIT CONFIGURATION
The PWM output unit configuration is shown in Figure 13-1.
8
PWMn
15
PWPR
f
PWMC
f
Prescaler
8-Bit Down-Counter
CLK
Remark n = 0, 1
(1) 8-bit down-counter
Generates the basic PWM signal timing.
(2) PWM pulse generator (including 4-bit counter)
Controls addition of extra pulses and generates the PWM pulses to be output.
(3) Reload control
Controls 8-bit down counter and 4-bit count modulo value reloading.
(4) Output control circuit
Controls the active level of the PWM signal.
(5) Prescaler
Scales f
, and generates the reference clock.
CLK
378
CHAPTER 13 PWM OUTPUT UNIT
Figure 13-1 PWM Output Unit Configuration
Internal Bus
16
8
7
4
8
4
Reload
PWM Pulse
Generator
1/256
4-Bit Counter
User's Manual U11316EJ4V1UD
3
0
PWMC
Reload
Reload Control
Output Control
Circuit
8
P1n/
PWMn
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