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(1) Internal high-speed RAM (IRAM)
The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode for high-
speed accesses can be used on FD20H to FEFFH in this area. There are two kinds of short direct addressing mode, short
direct addressing 1 and short direct addressing 2, according to the target address. The function is the same in both of these
addressing modes. With some instructions, the word length is shorter with short direct addressing 2 than with short direct
addressing 1. See the 78K/IV Series User's Manual Instruction Volume for details.
A program fetch cannot be performed from IRAM. If a program fetch is performed from an address onto which IRAM is
mapped, CPU inadvertent loop will result.
The following areas are reserved in IRAM.
• General-purpose register area : FE80H to FEFFH
• Macro service control word area : FE06H to FE2FH (excluding 0FE22H, 0FE23H, 0FE2AH, 0FE2BH)
• Macro service channel area
If the reserved function is not used in these areas, they can be used as ordinary data memory.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed. When the
LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.
(2) Peripheral RAM (PRAM)
The peripheral RAM (PRAM) is used as ordinary program memory or data memory. When used as program memory, the
program must be written to the peripheral RAM beforehand by a program.
Program fetches from peripheral RAM are fast, with a 2-byte fetch being executed in 2 clocks.
3.4.2 Special Function Register (SFR) Area
The on-chip peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to 0FFFFH (see
Figures 3-1 to 3-5).
The area from 0FFD0H to 0FFDFH is mapped as an external SFR area, and allows externally connected peripheral I/Os,
etc., to be accessed in external memory extension mode (specified by the memory extension mode register (MM)) by the ROM-
less product or on-chip ROM products.
Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an address is
accessed by mistake, the CPU may become deadlocked. A deadlock can only be released by reset input.
Remark The addresses in this text are those that apply when the LOCATION 0H instruction is executed. When the
LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.
3.4.3 External SFR Area
In µ PD784038 Subseries products, the 16-byte area from 0FFD0H to 0FFDFH in the SFR area (when the LOCATION 0H
is executed; 0FFFD0H to 0FFFDFH when the LOCATION 0FH instruction is executed) is mapped as an external SFR area.
When the external memory extension mode is set in a ROM-less product or on-chip ROM product, externally connected
peripheral I/Os, etc., can be accessed using the address bus or address/data bus, etc.
As the external SFR area can be accessed by SFR addressing, peripheral I/O and similar operations can be performed easily,
the object size can be reduced, and macro service can be used.
Bus operations for accesses to the external SFR area are performed in the same way as for ordinary memory accesses.
82
CHAPTER 3 CPU ARCHITECTURE
: FE00H to FEFFH (the address is specified by the macro service control word)
User's Manual U11316EJ4V1UD
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