Watchdog Timer Mode Register (Wdm) - NEC uPD784038 Series User Manual

12.2 WATCHDOG TIMER MODE REGISTER (WDM)

The WDM is an 8-bit register that controls the watchdog timer operation.
To prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by
a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special code configuration (4 bytes), and a
write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements.
If the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt
is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source
of the error, and thus the address that was the source of the error can be identified from the return address saved in the
stack area.
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.
As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics
assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system
initialization should be performed by the program.
Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any
operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.
After a system reset (RESET input), once the watchdog timer has been started (by setting (to 1) the RUN bit), the WDM
contents cannot be changed. The watchdog timer can only be stopped by a reset, but can be cleared at any time with a
dedicated instruction.
The WDM can be read at any time by a data transfer instruction.
RESET input clears the WDM to 00H.
The WDM format is shown in Figure 12-2.
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CHAPTER 12 WATCHDOG TIMER FUNCTION
User's Manual U11316EJ4V1UD