Chapter 4 Clock Generator; Configuration And Function - NEC uPD784038 Series User Manual

4.1 CONFIGURATION AND FUNCTION

The clock generator generates and controls the internal clock and internal system clock supplied to the CPU and on-chip
hardware. The clock generator block diagram is shown in Figure 4-1.
EXTC OSTS2
X1
Clock Oscillator
X2
Remark f : Crystal/ceramic oscillation frequency or internal clock frequency
XX
f : Internal system clock frequency
CLK
The clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the X1 and X2 pins. When
standby mode (STOP) is set, oscillation stops (see CHAPTER 24 STANDBY FUNCTION).
It is also possible to input an external clock. In this case, the clock signal is input to the X1 pin, and the inverse phase signal
to the X2 pin.
The frequency divider generates an internal system clock by 1/2, 1/4, 1/8, or 1/16 scaling of the clock oscillator output (f
according to the setting of the standby control register (STBC).
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CHAPTER 4 CLOCK GENERATOR

Figure 4-1 Clock Generator Block Diagram
Internal Bus
OSTS
OSTS1 OSTS0 RESET
f /2
XX
f
XX
f /4
XX
Frequency
Divider f /8
XX
f /16
XX
User's Manual U11316EJ4V1UD
STBC
CK1 CK0 STP HLT
f
CLK
Selector
Internal System Clock
(CPU, Watchdog Timer, Noise Elimination
Circuit, A/D, PWM, Interrupts, Local Bus Interface)
f /2
XX
Internal Clock
(UART/IOE, CSI, Noise Elimination Circuit,
Timer/Counters, Oscillation Stabilization Timer)
RESET
)
XX