A/D Converter Mode Register (Adm) - NEC uPD784038 Series User Manual

14.2 A/D CONVERTER MODE REGISTER (ADM)

ADM is an 8-bit register that controls A/D converter operations.
The ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format
is shown in Figure 14-3.
Bit 0 (MS) controls the operating mode.
Bits 1, 2 and 3 (ANI0, 1, 2) select the analog inputs for A/D conversion.
Bit 5 (SCMD) controls the A/D conversion operation in scan mode.
Bit 6 (TRG) enables external synchronization of the A/D conversion operation. If the TRG bit is set (to 1) when the CS
bit is set (to 1), the conversion operation is initialized with each input of a valid edge as an external trigger to the INTP5
pin. When the TRG bit is cleared (to 0), the conversion operation is performed without regard to the INTP5 pin.
Bit 7 (CS) controls the A/D conversion operation. When the CS bit is set (to 1) the conversion operation is started, and
when cleared (to 0), all conversion operations are stopped even if conversion is in progress. In this case, the A/D conversion
result register (ADCR) is not updated and an INTAD interrupt request is not generated. Also, the power supply to the voltage
comparator is stopped, and the A/D converter power consumption is reduced.
RESET input clears the ADM register to 00H.
Caution When the STOP mode or IDLE mode is used, the power consumption should be reduced by clearing
(to 0) the CS bit before entering the STOP or IDLE mode. If the CS bit remains set (to 1), the conversion
operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage
comparator will not be stopped, and therefore the A/D converter power consumption will not be
reduced.
CHAPTER 14 A/D CONVERTER
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