Block Diagram - NEC uPD784038 Series User Manual

1.5 BLOCK DIAGRAM

Programmable
NMI
Interrupt
INTP0 to INTP5
Controller
INTP3
Timer/Counter 0
TO0
TO1
Timer/Counter 1
INTP0
INTP1
Timer/Counter 2
INTP2/CI
TO2
TO3
Timer 3
(16 Bits)
P00 to P03
Real-Time
Output Port
P04 to P07
PWM0
PWM1
ANO0
ANO1
AV Converter
REF2
AV
REF3
ANI0 to ANI7
AV
DD
AV
REF1
Converter
AV
SS
INTP5
1. The µ PD784038Y Subseries supports the I
Notes
2. When the µ PD784031, CLKOUT, P40 to P47, P50 to P57, P64, and P65 cannot be used.
Remark The capacities of the internal ROM and RAM differ depending on the model.
50
CHAPTER 1 GENERAL
(16 Bits)
(16 Bits)
(16 Bits)
78K/IV
CPU Core
RAM
PWM
D/A
A/D
User's Manual U11316EJ4V1UD
UART/IOE2
Baud-Rate
Generator
UART/IOE1
Baud-Rate
Generator
Clocked
Clock Output
ROM
Watchdog
Timer
2
C bus mode.
RxD/SI1
TxD/SO1
ASCK/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SCK0/SCL
Note 1
Serial SO0/SDA
Interface
SI0
ASTB/CLKOUT
AD0 to AD7
A8 to A15
A16 to A19
Bus I/F
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
Port 0
P00 to P07
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4 Note 2
P40 to P47
Port 5 Note 2
P50 to P57
Port 6
Note 2
P60 to P67
Port 7
P70 to P77
RESET
System
TEST
Control X1
X2
V , V
DD0 DD1
V , V
SS0 SS1
Note 2