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8.7.3 PWM Output
(1) Basic operation of PWM output
In this mode, a PWM signal with the period in which timer register 0 (TM0) reaches a full count used as one cycle is output.
The timer output (TO0) pulse width is determined by the value of compare register (CR00), and the timer output (TO1) pulse
width is determined by the value of compare register (CR01). When this function is used, the CLR01 bit of capture/compare
control register 0 (CRC0) must be set to 0.
The pulse cycle and pulse width are as shown below.
• PWM cycle = 65,536 × x/f
• PWM pulse width = CR0n × x/f
Note
0 cannot be set in the CR0n.
PWM pulse width
• Duty =
PWM cycle
Remark n = 0, 1
Timer Count
Count Start
0H
Interrupt
TO0
Remark ALV0 = 0
CHAPTER 8 TIMER/COUNTER 0
Table 8-7 TO0, TO1 Toggle Output (f
Count Clock
Minimum Pulse Width
0.25 µ s
8/f
XX
0.50 µ s
16/f
XX
1.00 µ s
32/f
XX
2.00 µ s
64/f
XX
4.00 µ s
128/f
XX
8.00 µ s
256/f
XX
16.00 µ s
512/f
XX
32.00 µ s
1,024/f
XX
64.00 µ s
2,048/f
XX
XX
Note
; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048
XX
CR0n
=
65,536
Figure 8-17 PWM Pulse Output
FFFFH
CR00
Pulse
Width
Pulse Cycle
User's Manual U11316EJ4V1UD
= 32 MHz)
XX
Maximum Interval Time
16.40 ms
32.80 ms
65.50 ms
131 ms
262 ms
524 ms
1.05 s
2.10 s
4.19 s
FFFFH
CR00
CR00
Pulse Width
Pulse Cycle
FFFFH
211
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