Development Board Setup; Setting Up The Development Board - Intel Stratix 10 GX User Manual

3 Development Board Setup

3 Development Board Setup
The instructions in this chapter explain how to setup the Intel Stratix 10 GX
Transceiver Signal Integrity Development Board.

3.1 Setting up the Development Board

To prepare and apply power to the board, perform the following steps:
1. The Intel Stratix 10 GX transceiver signal integrity development kit ships with its
board switches preconfigured to support the design examples in the kit. If you
suspect your board might not be correctly configured with the default settings,
follow the instructions in the
8 to return the board to its factory settings before proceeding.
2. The development kit ships with design examples stored in the flash device. The
POWER-ON slide switch (SW7) is provided to turn the board ON or OFF.
Caution: When the power cord is plugged into connector J103 of the Intel Stratix
3. Set the
board, three green LEDs (D29, D31 and D32) illuminate and an amber LED
(D36) extinguishes indicating that the board has power. If the amber LED (D36)
illuminates, it indicates that one or more power supply is incorrect.
4. RESET button (S12) is connected to the MAX V CPLD (
used for AvST configuration. When this button is pressed, the MAX V CPLD
initiates a reloading of the stored image from the flash memory using AvST
configuration mode. The image loaded right after power cycle or MAX V reset
depends on
• OFF(1) - factory load
• ON (0) - user defined load #1
Page selection can be changed by the
powered on, and
corresponding page which is indicated by
Caution: Use only the supplied power supply. Power regulation circuits on the
The MAX V CPLD device on the board contains a parallel flash loader II (PFL II)
megafunction. After a
configures the Intel Stratix 10 FPGA in AvST mode with either factory design or user
design depending on the setting of
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Factory Default Switch and Jumper Settings
10 transceiver signal integrity development kit,
are present on to the board with switch SW7 in the 'OFF' position.
These voltages are restricted to a small area of the board. When switch
SW7 is placed to 'ON' position, all voltages planes have power at this
point.
switch SW7 to the ON position. When power is supplied to the
POWER-ON
settings.
FACTORY_LOAD
PGM_CONFIG
board can get damaged by power supplies with greater voltage.
or
POWER-ON
button (S10) when the board is
PGMSEL
(S11) is used to reconfigure FPGA with
,
PGM_LED0 PGM_LED1
(reconfiguration) event, the MAX V CPLD
RESET
.
FACTORY_LOAD
on page
and
12V_IN 3.3V_STBY
pin) that is
MAX_RESETn
or
PGM_LED2
ISO
9001:2008
Registered
.