Figure 6-10. Pcie Endpoint Connections Example - Nvidia Jetson Xavier NX Design Manual

Figure 6-10. PCIe Endpoint Connections Example

SoC - PCIe
NVHS
NVHS_TX3_N
NVHS_TX3_P
NVHS_RX3_N
NVHS_RX3_P
NVHS_TX2_N
NVHS_TX2_P
NVHS_RX2_N
NVHS_RX2_P
NVHS_TX1_N
NVHS_TX1_P
NVHS_RX1_N
NVHS_RX1_P
NVHS_TX0_N
NVHS_TX0_P
NVHS_RX0_N
NVHS_RX0_P
See Note 1
NVHS0_REFCLK_N
NVHS0_REFCLK_P
PEX
PEX_CLK5_N
PEX_CLK5_P
PEX
Control
PEX_WAKE_N
PEX_L5_CLKREQ_N
PEX_L5_RST_N
AO_HV
CAN0_EN
Notes:
1. For Endpoint operation, the mux should be set to input the reference clock from the PCIe Root
Port device to the Jetson Xavier NX NVHS0_REFCLK pins. CAN0_EN which is used for the mux
select should be set high.
2. AC capacitors required on RX lines on carrier board if connected directly to device. They
should not be on the carrier board if connected to PCIe connector, M.2 Key M, etc. In those
cases, the AC caps are on the board connected to those connectors.
3. See design guidelines for correct AC capacitor values.
4. Open-drain buffers are required on the PCIe control signals when Jetson Xavier NX is
configured as Endpoint. These isolate the lines from the on-module pull-ups as well as
ensure the Endpoint and Root Port devices do not have their pads driven high before power is
applied (3V3_RP is 3.3V supply on the Root Port side and 3V3_EP is the 3.3V supply on the
Endpoint side.
5. The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification
"REFCLK DC Specifications and AC Timing Requirements." The clocks are HCSL compatible.
NVIDIA Jetson Xavier NX
Jetson
PCIE0_TX3_N
PCIE0_TX3_P
PCIE0_RX3_N
PCIE0_RX3_P
PCIE0_TX2_N
PCIE0_TX2_P
PCIE0_RX2_N
PCIE0_RX2_P
PCIE0_TX1_N
PCIE0_TX1_P
PCIE0_RX1_N
PCIE0_RX1_P
PCIE0_TX0_N
PCIE0_TX0_P
PCIE0_RX0_N
PCIE0_RX0_P
PCIE0_CLK_N
PCIE0_CLK_P
Mux
CAN0_EN
SEL
3.3V
PCIE_WAKE*
PCIE0_CLKREQ*
PCIE0_RST*
NVHS0_REFCLK/PEX_CLK5
Mux Control
See Note 2
154
156
PCIe 0 Lane 3
155
157
148
150
PCIe 0 Lane 2
149
151
140
142
PCIe 0 Lane 1
137
139
134
136
PCIe 0 Lane 0
131
133
160
162
3V3_RP
OD
3V3_EP
OD
179
180 OD
181
See Note 4
OD
DG-09693-001_v1.7 | 28
USB and PCIe
PCIe 0 (Ctrl
#5) – PCIe x4
Endpoint
PCIe 0 (Ctrl
#5) – PCIe x4
Endpoint