Nvidia Jetson AGX Xavier Series Design Manual
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Nvidia Jetson AGX Xavier Series Design Manual

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Jetson AGX Xavier Series Product
Design Guide
DG-09840-001_v2.5
|
December 2021

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Summary of Contents for Nvidia Jetson AGX Xavier Series

  • Page 1 Jetson AGX Xavier Series Product Design Guide DG-09840-001_v2.5 December 2021...
  • Page 2 Removed level shifter on USB Micro ID signal and • added note PCIe Updated PCIe figure and table Root Port and added • PEX_L5 control. Updated PCIe RST pull-up value figure/table and • checklist. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | ii...
  • Page 3 Updated USB Micro AB Connection figure • PCIe Updated PEX_WAKE_N usage in Pin Description tables • Corrected connection figures for for • NVHS0_SLVS_REFCLK Updated figure module pin #s/names for UFS CLK/RST. • MIPI CSI Jetson AGX Xavier Series Product DG-09840-001_v2.5 | iii...
  • Page 4 EP not supported on C0 and C4 in Table 7-14 Added NVHS0_SLVS_REFCLK_N/P pin to Table 7-14 • Removed C0 and C4 from Table 7-15 as these are no longer • supported as Eps Jetson AGX Xavier Series Product DG-09840-001_v2.5 | iv...
  • Page 5 Description to indicate I2S6 (DAP6 on SoC) is not supported for JAXi. December 2, 2021 Corrected Table 2-2 (Pinout Matrix) to have GPIO12 (pin E10) • called out for Safety MCU usage Jetson AGX Xavier Series Product DG-09840-001_v2.5 | v...
  • Page 6 Corrected SoC pin name for GPIO05 for JAXi. • Updated USB Recovery Mode section to include minimum • requirements for entering recovery mode. Updated title of AN for Boundary scan in Debug and • Strapping sections. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | vi...

  • Page 7: Table Of Contents

    Signal Name Conventions ....................34 Routing Guideline Format ....................35 Signal Routing Conventions ..................... 35 Routing Guidelines ......................35 General PCB Routing Guidelines ..................36 Chapter 7. USB, PCIe, and UFS ................37 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | vii...
  • Page 8 13.3 UART ..........................110 13.4 CAN ..........................112 Chapter 14. Fan ....................114 Chapter 15. Debug and Strapping ................ 116 15.1 USB Recovery Mode ....................... 116 15.2 JTAG and Debug UART ....................117 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | viii...
  • Page 9 21.2.1 Microstrip Transmission Line ................. 132 21.2.2 Stripline Transmission Line ..................132 21.3 Drive Characteristics ..................... 133 21.4 Receiver Characteristics ....................133 21.5 Transmission Lines and Reference Planes ..............134 Chapter 22. Design Guideline Glossary ..............137 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | ix...
  • Page 10 Chapter 23. USB SS and Wireless Coexistence ............ 139 23.1 Mitigation Techniques ....................139 Chapter 24. Jetson AGX Xavier Pin Description ............ 141 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | x...
  • Page 11 Figure 9-4. HDMI CLK and Data Topology ................71 Figure 10-1. Camera Control Connections ................84 Figure 10-2. Camera CSI D-PHY Connections ................. 85 Figure 10-3. Camera CSI C-PHY Connections ................. 86 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xi...
  • Page 12 Power Plane Cuts Example ................135 Figure 21-7. Power Plane Cuts Example when Decouple Capacitors are abundant ..135 Figure 21-8. Switching Reference Planes ................136 Figure 21-9. Reference Plane Switch Using Via ..............136 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xii...
  • Page 13 Jetson AGX Xavier Gigabit Ethernet Pin Descriptions ........59 Table 8-2. RGMII Interface Signal Routing Requirements ..........61 Table 8-3. Ethernet MDI Interface Signal Routing Requirements ........61 Table 8-4. Ethernet Signal Connections ................62 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xiii...
  • Page 14 I2C Interface Mapping ..................104 Table 13-3. I2C Interface Signal Routing Requirements ............. 106 Table 13-4. I2C Signal Connections ..................106 Table 13-5. De-bounce Settings – Fast Mode Plus, Fast Mode, and Standard Mode ..107 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xiv...
  • Page 15 Strapping Pins ....................119 Table 15-5. Safety MCU Related Partial Pin Descriptions ........... 121 Table 16-1. MPIO Maximum Output Drive Current .............. 124 Table 17-1. Unused MPIO Pins and Pin Groups ..............125 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xv...

  • Page 16: Chapter 1. Introduction

    Refer to software release documentation for information on supported capabilities. Note: References to Jetson AGX Xavier applies to any of the Jetson AGX Xavier series of modules including Jetson AGX Xavier Industrial (JAXi) except where explicitly noted.

  • Page 17: Table 1-1. Abbreviations And Definitions

    Physical Layer PMIC Power Management IC Real Time Clock SDIO Secure Digital I/O Interface SLVS Scalable Low Voltage Signaling Serial Peripheral Interface UART Universal Asynchronous Receiver-Transmitter Universal Flash Storage Universal Serial Bus Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 2...

  • Page 18: Chapter 2. Jetson Agx Xavier

    JTAG and UART Digital Mic and Speaker IFs System Power control, Reset, Alerts Power Main Inputs (HV and MV) UART Note: HDMI and DP share the same pins. See Chapter 9 for display details. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 3...

  • Page 19: Figure 2-1. System Block Diagram

    RGMII TEMP_ALERT_OUT (See note 1) PWM 4x Notes: 1. SPI2, RGMII, GPIO31, and GPIO33 are available to use with a Safety MCU. 2. PCIe x8 interface and SLVS share the same pins. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 4...

  • Page 20: Table 2-2. Connector Pinout Matrix Part 1: Columns A-F

    RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD CSI0_D1_N RSVD RSVD CSI0_D1_P RSVD RSVD RSVD CSI2_D0_P CSI2_D1_N CSI0_D0_N CSI2_D0_N CSI2_CLK_N CSI2_D1_P CSI5_D0_P CSI0_D0_P CSI0_CLK_N CSI2_CLK_P CSI5_D0_N CSI0_CLK_P CSI7_D0_P CSI5_CLK_P CSI3_D0_N Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 5...

  • Page 21: Table 2-3. Connector Pinout Matrix Part 2: Columns G-L

    PEX_L3_ RSVD FORCE_ CLKREQ_N RECOVERY_N USB3_P RSVD STANDBY_REQ_N UPHY_TX11_P UPHY_TX10_N UPHY_TX11_N UPHY_TX10_P UPHY_TX9_N UPHY_TX8_P I2S1_CLK UPHY_TX9_P UPHY_TX8_N GPIO14 UPHY_TX7_P UPHY_TX6_N UPHY_TX7_N UPHY_TX6_P UPHY_TX5_N UPHY_TX4_P RSVD UPHY_TX5_P UPHY_TX4_N RSVD UPHY_TX3_P UPHY_TX2_N UPHY_TX3_N UPHY_TX2_P Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 6...
  • Page 22 SYS_VIN_HV PRSNT1 SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV Legend Ground Power Reserved – Must be left unconnected No pins at that JAXi only Safety MCU unless otherwise directed. location usage on JAXi Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 7...

  • Page 23: Chapter 3. Main Connector Details

    Note: Various documents related to the Molex Mirror Mezz connector can be found at: https://www.molex.com/molex/products/datasheet.jsp?part=active/2034560003_PCB_HEADERS .xmlandchannel=ProductsandLang=en-US.The Molex Application Guide for Mirror Mezz which ™ includes details for connector mounting can be found at: https://www.molex.com/pdm_docs/as/2028280001-AS-000.pdf Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 8...

  • Page 24: Connector Pin Orientations

    Figure 3-2. 699-pin Connector Pin Orientations Pin A63 Pin A3 (GND) (PRSNT0) Pin L3 Pin L63 (GND) (PRSNT1) Pin L63 Pin L3 (PRSNT1) (GND) Pin A3 Pin A63 (PRSNT0) (GND) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 9...

  • Page 25: Module To Carrier Board Spacing Details

    Notes: See Section 3.3 on recommendations for standoff heights. If the Molex Part # 2048430001, 2.5 mm height connector is used, there can be no components under the module on the carrier board due to the extremely limited clearance. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 10...

  • Page 26: Module To Carrier Board Standoff Height Recommendations

    The connector contact sweep range can be found on the Molex website in the Mirror Mezz area. Jetson AGX Xavier Data Sheet The module bottom plate height/tolerance can be found in the Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 11...

  • Page 27: Module Installation And Removal

    See additional notes in the “Notes” section of Table 3-1. Module Installation and Removal To install the Jetson AGX Xavier Series module correctly, follow the following sequence and mounting hardware instructions: Connectors should be parallel with respect to each other during mating.

  • Page 28: Figure 3-5. Module Removal

    ± 2 degrees. Also, the fixture should allow the connectors to become parallel as the mating process progresses. To remove the Jetson AGX Xavier Series module correctly, follow the following sequence and mounting hardware instructions: The PCB design needs to have enough finger reachability/space required to hold the board for un-mating.

  • Page 29: Chapter 4. Reference Design Considerations

    This chapter describes details necessary for designers to know to replicate certain features if desired. In addition, aspects of the design that are specific to the NVIDIA developer kit usage but not useful or supported on a custom carrier board are also identified.
  • Page 30 NVIDIA. The ID EEPROM (P2822 – U501) is a feature that is used for NVIDIA internal purposes, but ...

  • Page 31: Chapter 5. Power

    Chapter 5. Power This chapter describes the power specifications for the Jetson AGX Xavier Series module. CAUTION: Jetson AGX Xavier is not hot-pluggable. Before installing or removing the module, the main power supply (to SYS_VIN_HV and SYS_VIN_MV pins) must be disconnected and the power rails allowed to discharge to <0.6V.
  • Page 32 In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. The output voltage is configurable in the PMIC. It can be disabled if a non-rechargeable source is connected, or set to 2.5V, 3.0V, 3.3V or 3.5V. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 17...

  • Page 33: Supply Allocation

    VDDIO_AO_1V8 See Note 4 PMIC Switcher SD3 SYS_VIN_MV DDR_AP_1V1 SoC VDDIO_DDRx rail PMIC Switcher SD4 SYS_VIN_MV VDD_RTC SoC RTC rail Variable PMIC LDO0 SYS_VIN_MV DDR_VDD2_ See Note 5 PMIC LDO1 SYS_VIN_MV 1V1_EN Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 18...

  • Page 34: Power Sequencing

    If the carrier board supplies required for powering on require additional time, the signal can be held low. This will keep the PERIPHERAL_RESET_N SoC and other boot devices in reset. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 19...

  • Page 35: Figure 5-2. Power Up Sequence - Power Button Case

    One way is to latch the state of CARRIER_POWER_ON when it goes from high to low (module powered off) and using this to keep MODULE_POWER_ON inactive (low). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 20...

  • Page 36: Figure 5-3. Power Down Sequence Controlled Case

    Power Down Sequence Uncontrolled Case SYS_VIN_HV (VCC_SRC) SYS_VIN_MV VDDIN_PWR_BAD_N SYS_RESET_N VIN_PWR_ON CARRIER_POWER_ON Carrier Board System Power MODULE_POWER_ON Module Power Note: SYS_VIN_MV must go below 100 mV before system can be powered on again. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 21...

  • Page 37: Sys_Vin_Hv Input

    DC power jack, the circuit in the following figure can be used. Note: Designs that intend to follow the NVIDIA carrier board design and include the Type C PD Controller (CYPD4226 - U513 on NVIDIA carrier board) need to replicate the circuitry on the latest P2822 carrier board exactly.

  • Page 38: Auto Power-On Option No Mcu

    For designs that will not have a power button but should power on when the main power supply is connected, the optional ACOK circuit shown in Figure 5-7 should be implemented and the signal pulled to ACOK_L Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 23...

  • Page 39: Power Button Supervisor Mcu Power-On

    EFM8SB10F8G-A-QFN20 MPU for Button Power Button control need to replicate the circuitry on the latest P2822 carrier board exactly. NVIDIA will provide the binary and the customer should get the flashing instructions from Silicon Labs. Otherwise, another solution such as the one described earlier in the Power-On (No MCU) can be used.

  • Page 40: Defined Behaviors

    ), will have the same (brief) duration of the Power Button input to the MCU. Once POWER_BTN_N the power button is pressed, the power OK input (ACOK) is ignored, as the power ON sequence is already initiated by the power button. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 25...

  • Page 41: Power Off -> Power On (Auto-Power-On Case)

    ACOK is driven high (by push-pull driver powered from 3V3_AO), the power button signals will not affect the MCU behavior until the signal verification is complete. PWR_GOOD Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 26...

  • Page 42: Power On -> Power Off (Power Button Held Low > 10 Seconds)

    With the system in power ON state, the user holds the power button for more than 10 seconds. The same button signal is relayed to Jetson AGX Xavier through the buffered signal . The system is forced to shut down at the 10 seconds mark. POWER_BTN_N Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 27...

  • Page 43: Power Discharge

    It is recommended that the circuit be kept as shown to provide the most margin for properly sequencing power off during sudden power removal cases. If the supply cannot maintain the Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 28...
  • Page 44 ~0.5V. By adding one diode, an additional 0.6V-0.7V droop would be allowed. This will reduce the benefit that the DV/Dt circuit provides and should be avoided if possible or kept to a minimum (one additional diode). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 29...

  • Page 45: Power And Voltage Monitoring

    This section describes the power and voltage monitoring for Jetson AGX Xavier. 5.6.1 Power Loss Detection The circuit in Figure 5-13 is implemented on the NVIDIA Jetson AGX Xavier carrier board to detect a loss or unacceptable droop on the main power input ( VCC_SRC Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 30...

  • Page 46: Power Monitor

    (DDRQ supply input) 20Ω SYS 5V_P SYS _VIN_ MV VIN3P 665 kΩ Sys tem 5V Supply Monitor 0.005Ω, 1% VDD_SYS _5V0 20Ω WARN VIN3N 080 5 SYS 5V_N (SY S_VIN_MV input) CRIT Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 31...

  • Page 47: Deep Sleep Or Sc7

    SPI 1 Chip Select 1 (SPI1_CS1#) SPI1_CS1_N Wake50 Fan Tachometer (FAN_TACH) FAN_TACH Wake51 UART 1 Clear to Send (UART1_CTS) UART2_CTS Wake52 UART 2 Clear to Send (UART2_CTS) UART5_CTS Wake53 PCIe L1 Clock Request (PEX_L1_CLKREQ_N) PEX_L1_CLKREQ_N Wake54 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 32...
  • Page 48 Wake65 GPIO 6(CVB_GPIO6) GPIO24 Wake66 Force Recovery (FORCE_RECOVERY) FORCE_RECOVERY_N Wake67 Sleep (SLEEP#) STANDBY_REQ_N Wake68 Battery Low (BATLOW#) GPIO28 Wake69 HDMI Consumer Electronics Control (HDMI_CEC) HDMI_CEC Wake70 DP 2 Hot-Plug-Detect (DP2_HPD) DP2_HPD Wake71 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 33...

  • Page 49: Chapter 6. General Routing Guidelines

    Signal Type Codes Code Definition Analog DIFF I/O Bidirectional Differential Input/Output DIFF IN Differential Input DIFF OUT Differential Output Bidirectional Input/Output Input Output Open Drain Output I/OD Bidirectional Input / Open Drain Output Power Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 34...

  • Page 50: Routing Guideline Format

    Each interface has different trace impedance requirements and spacing to other traces. It is up to designer to calculate trace width and spacing required to achieve specified single- ended (SE) and differential (Diff) impedances. Unless otherwise noted, trace impedance values are ±15%. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 35...

  • Page 51: General Pcb Routing Guidelines

    Do not route other signals or power traces and areas directly under or over critical high-speed interface signals. Note: The requirements detailed in the interface signal routing requirements tables must be met for all interfaces implemented or proper operation cannot be guaranteed. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 36...

  • Page 52: Chapter 7. Usb, Pcie, And Ufs

    UPHY_RX6_N PEX_RX6_N UPHY Receive 6. USB 3.1 port 0. USB Type C Alt Mode Switch UPHY_RX6_P PEX_RX6_P UPHY_RX7_N PEX_RX7_N UPHY Receive 7. PCIe x1 controller #3. M.2 Key E Connector UPHY_RX7_P PEX_RX7_P Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 37...

  • Page 53: Table 7-3. Nvhs For Pcie X8 Data Lan Pin Descriptions

    PCIe/SLVS 0 Receive Lane 4. PCIe x8 controller #5 or SLVS, lane 4. NVHS0_SLVS_RX4_P NVHS0_RX4_P NVHS0_SLVS_RX5_N NVHS0_RX5_N PCIe/SLVS 0 Receive Lane 5. PCIe x8 controller #5 or SLVS, lane 5. NVHS0_SLVS_RX5_P NVHS0_RX5_P NVHS0_SLVS_RX6_N NVHS0_RX6_N Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 38...

  • Page 54: Table 7-4. Pcie Clock And Control Pin Descriptions

    PEX_CLK5_P PEX_CLK5P Jetson AGX Xavier used as Endpoint. PEX_L5_ PEX_L5_ PCIe 5 Clock Request for controller #5. Input Input Open-Drain – CLKREQ_N CLKREQ_N when Jetson AGX Xavier is Root Port. Output 3.3V Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 39...

  • Page 55: Table 7-5. Ufs And Miscellaneous Usb Control Pin Descriptions

    1 x1 PCIe x1 USB 3.1 PCIe x4 USB 3.1 PCIe x1 PCIe x2 UFS x1 USB 3.1 PCIe x8 x4 & 1 x8 (C1) (P2) (C0) (P0) (C3) (C4) (P3) (C5) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 40...

  • Page 56: Usb

    USB 3.1/2.0 connection to a USB 3.1 Type A connector or to replicate the USB Type C connections used on the NVIDIA Developer Kit. Designs that intend to follow the NVIDIA Developer Kit carrier board design and include the Type C PD Controller (CYPD4226) need to replicate the circuitry on the latest P2822 carrier board exactly.

  • Page 57: Figure 7-2. Jetson Agx Xavier Carrier Board Design Usb Type C Connection Example

    The load switch supplying VBUS should have over current protection. In the figure above this is supported • by routing the over current (OC) pin of the load switch to the GPIO22 (USB_VBUS_EN0) pin which is bidirectional and can be used to detect an over current condition. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 42...

  • Page 58: Usb 2.0 Design Guidelines

    ≥ -5.4 @ 5GHz (Host) / 2.5GHz (Device) mode) The resonance dip could be caused by a via stub for layer transition or trace stub for co- > 8 layout. Resonance Dip Frequency Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 43...
  • Page 59 The breakout trace width is suggested to be the minimum to increase inter-pair spacing Do not perform serpentine routing for intra-pair skew compensation in the breakout region Min Inter-SNEXT (between TX/RX) This is the recommended dimensions for meeting the NEXT requirement. Breakout 4.85x Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 44...
  • Page 60 Min A Spacing Trace width adjacent pair Min B, C Length 1.5x Min Jog Width Add-on Components Placement order SoC – AC capacitor – Common mode choke – ESD – Device/Connector AC Cap Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 45...

  • Page 61: Common Usb Routing Guidelines

    PCBs and flexes must be used for the max trace and skew calculations. Keep critical USB related traces away from other signal traces or unrelated power traces and areas or power supply components. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 46...

  • Page 62: Pci Express

    PCIe use. Root port is supported on all PCIe interfaces. Endpoint mode is supported on Interface C5 only. Figure 7-4 shows all the PCIe interfaces configured as Root Ports. Figure 7-5 shows C5 configured as an Endpoint. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 47...

  • Page 63: Figure 7-4. Pcie Root Port Connection Example

    See design guidelines for correct AC capacitor values. • The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification • “REFCLK DC Specifications and AC Timing Requirements.” The clocks are HCSL compatible. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 48...

  • Page 64: Figure 7-5. Pcie Endpoint Connection Example

    Control for PCIe I/F C5 PEX_L5_CLKREQ_N PEX_L5_RST_N PEX_L5_RST_N (PCIe x16 Connector on Carrier Board) Not used by PCIe I/F configured as Endpoint. PEX_WAKE_N PEX_WAKE_N Used for Root Port Wake only. Note: See “Notes” under Figure 7-4. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 49...

  • Page 65: Pcie Design Guidelines Up To Gen3

    Max # of Vias PTH Vias 2 for TX traces and 2 for RX trace Micro-Vias No requirement Max Via stub length Longer via stubs would require review Routing signals over antipads Not allowed Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 50...
  • Page 66 The average of the differential signals is used for length matching. Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 51...

  • Page 67: Figure 7-6. Insertion Loss S-Parameter Plot (Sdd21)

    USB, PCIe, and UFS Figure 7-6. Insertion Loss S-Parameter Plot (SDD21) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 52...

  • Page 68: Pcie Gen4 Design Guidelines

    Max PCB via distance from the 41.9 Max distance from Device ball or Connector Device/Connector pin to first PCB via. PCB within pair (intra-pair) skew 0.15 (0.5) mm (ps) Do trace length matching before hitting discontinuities. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 53...

  • Page 69: Table 7-14. Pcie Signal Connections Module I/Fs Configured As Root Ports

    Trace Impedance ±15% differential / Single Ended 85 / 50 Ω Reference plane Fiber-weave effect Example of zig-zag routing • Use spread-glass (denser weave) instead of regular-glass (sparse weave) to minimize intra-pair skew Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 54...
  • Page 70 3-4 mils larger than the pad size is required. Serpentine (See USB 3.1 Guidelines) Miscellaneous GND fill rule Remove unwanted GND fill that is either floating or act like antenna Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 55...

  • Page 71: Table 7-15. Pcie Signal Connections Module I/F Configured As Endpoint

    One for each of the PCIe TX_+/– output lines used. Near PCIe device. Connector pins may serve as test points if accessible. One for each of the PCIe RX_+/– input lines used. Near Jetson AGX Xavier connector. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 56...

  • Page 72: Ufs

    3x / 4x Length/Skew Breakout region (Max Length) 41.9 Minimum width and spacing. 4x or wider dielectric height spacing is preferred Max trace length Stripline 4 (700) In (ps) Microstrip 4 (600) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 57...

  • Page 73: Table 7-18. Ufs Signal Connections

    Note: Due to the power connections on the module, the SoC UFS sideband signal interface (UFS0_REF_CLK and UFS0_RST) supports 1.2V operation only. If higher voltage is required by the connected UFS device, level shifters will be needed. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 58...

  • Page 74: Chapter 8. Gigabit Ethernet

    EQOS_TXC Ethernet Transmit Clock Ethernet PHY Output CMOS – 1.8V Notes: In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 59...

  • Page 75: Figure 8-1. Ethernet Connections

    (1) TXD0+ RDP1 GBE_MDI3+ TRD3+ 75Ω TRD3- 100pF RDN1 GBE_MDI3– – – 10nF VDD_3V3 Note: The connections in Figure 8-2 match those used on the carrier board and are shown for reference. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 60...

  • Page 76: Table 8-2. Rgmii Interface Signal Routing Requirements

    Max Within Pair (Intra-Pair) Skew 0.15 (1) mm (ps) Number of Vias minimum Ideally there should be no vias, but if required for breakout to Ethernet controller or magnetics, keep very close to either device. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 61...

  • Page 77: Table 8-4. Ethernet Signal Connections

    Recommended Gigabit Ethernet Observation Test Points for Initial Boards Test Points Recommended Location One for each of the RGMII lines. One for each of the MDI[3:0]+/– lines. Near Jetson AGX Xavier connector and magnetics device. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 62...

  • Page 78: Chapter 9. Display

    HDMI_DP2_TXDN0 DisplayPort 2 Lane 0– or HDMI Lane 2– HDMI_DP2_TX0_P HDMI_DP2_TXDP0 DisplayPort 2 Lane 0+ or HDMI Lane 2+ HDMI Connector Output Diff pair HDMI_DP2_TX1_N HDMI_DP2_TXDN1 DisplayPort 2 Lane 1– or HDMI Lane 1– Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 63...

  • Page 79: Table 9-2. Dp And Hdmi Pin Mapping

    HDMI_DP1_TXDN0 TXD2_N TXD0_N HDMI_DP1_TX1_P HDMI_DP1_TXDP1 TXD1_P TXD1_P HDMI_DP1_TX1_N HDMI_DP1_TXDN1 TXD1_N TXD1_N HDMI_DP1_TX2_P HDMI_DP1_TXDP2 TXD0_P TXD2_P HDMI_DP1_TX2_N HDMI_DP1_TXDN2 TXD0_N TXD2_N HDMI_DP1_TX3_P HDMI_DP1_TXDP3 TXC_P TXD3_P HDMI_DP1_TX3_N HDMI_DP1_TXDN3 TXC_N TXD3_N HDMI_DP2 HDMI_DP2_TX0_P HDMI_DP2_TXDP0 TXD2_P TXD0_P Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 64...

  • Page 80: Dp And Edp

    DisplayPort specification for the modes to be supported. Any ESD solution must also maintain signal integrity and meet the DisplayPort requirements for the modes to be supported. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 65...

  • Page 81: Dp And Edp Routing Guidelines

    (Zdiff does not account for trace coupling) 95Ω should be used to support DP-HDMI co- layout as HDMI 2.0 requires 100Ω impedance (see HDMI section for addition of series resistor R Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 66...
  • Page 82 >= 1.2 mm center- center. Place GND via as symmetrically as GND via is used to maintain return path, while GND via possible to data pair vias. Up to 4 its Xtalk suppression is limited Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 67...
  • Page 83 The average of the differential signals is used for length matching. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or any discontinuity to minimize common mode conversion Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 68...

  • Page 84: Hdmi

    HDMI A standard DP 1.2a or HDMI v2.0 interface is supported. These share the same set of interface pins, so either DisplayPort or HDMI can be supported natively. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 69...

  • Page 85: Figure 9-3. Hdmi Connection Example

    HDMI interface is to be used. Chokes between pull-downs and FET are required for Standard Technology designs and recommended for HDI designs. 5. Series resistors RS are required. See the RS section of Table 9-6 for details. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 70...

  • Page 86: Figure 9-4. Hdmi Clk And Data Topology

    5.94 / 168 Gbps / ps Per lane – not total link bandwidth Topology Point to point Unidirectional, Differential Termination Differential To 3.3V at receiver At Receiver Ω To GND near connector On-board Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 71...
  • Page 87 See Notes 1, 2 and 3 Max GND transition Via distance Diff pair via pitch For signals switching reference layers, add one or two ground stitching vias. It is recommended they be symmetrical to signal vias. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 72...
  • Page 88 The traces after main-route via should be routed as 100Ω differential or as uncoupled 50ohm Single-ended traces on PCB Top or Bottom. Max distance from RPD to main trace (seg B) Max distance from AC cap to RPD stubbing point (seg A) Max distance between ESD and signal via Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 73...
  • Page 89 Differential TDR impedance 90ohm +/-15% @ Tr=200ps (10%- 90%) Min Sdd21 @ 2.5GHz 2.22 Max Scc21 @ 2.5GHz 19.2 Location Close to any adjacent discontinuity (< 8mm) – such as connector, via, etc. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 74...
  • Page 90 If routing includes a flex or 2nd PCB, the max trace delay and skew calculations must include all the PCBs/flex routing. Solutions with flex/2nd PCB may not achieve maximum frequency operation. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 75...

  • Page 91: Table 9-7. Hdmi Signal Connections

    Near display connector. Connector pins can be used if accessible. Note: Test points must be done carefully to minimize signal integrity impact. Avoid stubs and keep pads small and near signal traces. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 76...

  • Page 92: Chapter 10. Video Input

    Camera, CSI 0: DPHY Data 1+. CPHY CSI0_D1_P CSI_A_D1_P 01:A Camera, CSI 1: DPHY Clock–, CPHY CSI1_CLK_N CSI_B_CLK_N 11:C Camera, CSI 1: DPHY Clock+. CPHY CSI1_CLK_P CSI_B_CLK_P 10:C Camera, CSI 1: DPHY Data 0–. CPHY CSI1_D0_N CSI_B_D0_N 10:B Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 77...
  • Page 93 CSI_F_CLK_P 50:C Camera, CSI 5: DPHY Data 0–. CPHY CSI5_D0_N CSI_F_D0_N 50:B Camera, CSI 5: DPHY Data 0+. CPHY CSI5_D0_P CSI_F_D0_P 50:A Camera, CSI 5: DPHY Data 1–. CPHY CSI5_D1_N CSI_F_D1_N 51:B Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 78...
  • Page 94 The C-PHY pin mappings are programmable. See the Jetson (GMSL Interposer section) for details. In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 79...

  • Page 95: Table 10-2. Jetson Agx Xavier Camera Miscellaneous Pin Description

    Table 10-3. CSI Configurations D-PHY Mode x2 Configurations x4 Configurations Signal Name CSI_0_D0_P/N Data CSI_0_D1_P/N Data CSI_1_D0_P/N Data CSI_1_D1_P/N CSI_2_D0_P/N Data CSI_2_D1_P/N Data CSI_3_D0_P/N Data CSI_3_D1_P/N CSI_4_D0_P/N Data CSI_4_D1_P/N Data CSI_5_D0_P/N CSI_5_D1_P/N Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 80...
  • Page 96 Each 2-lane option shown in this table can also be used for one single lane camera as well. Combinations of 1, 2 and 4-lane cameras are supported, as long as any 4-lane cameras match one of the four configurations. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 81...

  • Page 97: Table 10-4. Csi Configurations C-Phy Mode - X2 And X4

    Notes: Each x2 configurations can also be used for one single lane camera (x1 configuration) as well. Configurations can coexist to support a mix of x1, x2 and x4 lanes, as long as each signal is not shared between multiple configurations. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 82...

  • Page 98: Table 10-5. Csi Configurations C-Phy - X3 And X1

    CSI_5_D0_P/N CSI_5_CLK_N, CSI_5_D1_P/N CSI_6_CLK_P, √ CSI_6_D0_P/N CSI_6_CLK_N, √ CSI_6_D1_P/N CSI_7_CLK_P, √ CSI_7_D0_P/N CSI_7_CLK_N, CSI_7_D1_P/N Notes: Each of the above blocks (x4) can be swapped for one of the 2x2 or 1x4 configurations. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 83...

  • Page 99: Figure 10-1. Camera Control Connections

    Note: Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing and Vil/Vih requirements at the receiver and maintain signal quality and meet requirements for the frequencies supported by the design. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 84...

  • Page 100: Figure 10-2. Camera Csi D-Phy Connections

    Note: Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing and Vil/Vih requirements at the receiver and maintain signal quality and meet requirements for the frequencies supported by the design. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 85...

  • Page 101: Figure 10-3. Camera Csi C-Phy Connections

    CSI6_D1_P CSI_G_D1_P CPHY_61_B CSI6_D1_N CSI_G_D1_N 3-Trios CPHY_61_C CSI6_CLK_N CSI_G_CLK_N 4-Trios CPHY_70_A CSI7_D0_P CSI_H_D0_P CPHY_70_B CSI7_D0_N CSI_H_D0_N CPHY_70_C CSI7_CLK_P CSI_H_CLK_P B4 5 CPHY_71_A CSI7_D1_P CSI_H_D1_P CPHY_71_B CSI7_D1_N CSI_H_D1_N CPHY_71_C CSI7_CLK_N CSI_H_CLK_N B4 6 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 86...

  • Page 102: Csi D-Phy Design Guidelines

    Up to 4 signal vias can share a single GND return via If routing to device includes a flex or 2nd PCB, the max trace and skew calculations must include all the PCBs/flex routing Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 87...

  • Page 103: Csi C-Phy Mode Design Guidelines

    Note: Depending on the mechanical design of the platform and camera modules, ESD protection may be necessary. In addition, EMI control may be needed. Both are shown in the Camera Connection Example diagram. Any EMI/ESD solution must be compatible with the frequency required by the design. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 88...

  • Page 104: Slvs Camera Interface

    Diff Pair NVHS0_SLVS_ pins are used for SLVS-EC NVHS0_REFCLK_P REFCLK0_P interface. NVHS0_SLVS_RX0_ UPHY/SLVS NVHS0_RX0_N Diff Pair, AC- PCIe/SLVS Receive Lane 0 PCIe x16 Connector Input Coupled on NVHS0_SLVS_RX0_ NVHS0_RX0_P carrier board if Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 89...
  • Page 105 The direction of the control signals in the table are for SLVS usage. If used as GPIOs, they support input or output (bidirectional). In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 90...

  • Page 106: Figure 10-4. Slvs Connections

    OUTP CLK_IN DIF0* 33Ω LVDS_72MHZ_N OUTN CLK_IN* EN/NC DIF1 NC/EN DIF1* GNDx Note: Direct lane mapping (RX[7:0] to DX[7:0] shown in Figure 10-4. Reverse mapping (RX[7:0] to DX[0:7]) has also been verified. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 91...

  • Page 107: Slvs Design Guidelines

    Keep critical traces away from other signal traces or unrelated power traces/areas or power supply components Note: If routing to device includes a flex or 2nd PCB, the skew calculations must include all the PCBs/flex routing Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 92...

  • Page 108: Table 10-13. Slvs Camera Signal Connections

    Differential Clock Buffer Output #1: Connect to GND on each line. 100Ω LVDS-CMOS device inputs. resistor between the P/N lines. LVDS-CMOS Output LVDS-CMOS converter output: Connect to SLVS device/connector input clock (INCK in figure) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 93...

  • Page 109: Chapter 11. Sdio And Sd Card

    Figure 11-1 shows a Micro SD card socket connection example. Internal pull-up resistors are used for SDCARD Data/CMD lines. External pull-ups are not required and cannot be used due to the internal pad voltage selection. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 94...

  • Page 110: Figure 11-1. Micro Sd Card Socket Connection Example

    Up to 4 signal Vias can share 1 GND return Via proximity (Signal to reference) Trace spacing – Microstrip / Stripline 4x / 3x dielectric Trace length SDR50 / SDR25 / SDR12 / HS / DS Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 95...

  • Page 111: Table 11-4. Sd Card Loading Vs. Drive Type

    LOAD CARD Drive Type = B Total load capacitance supported (CLK freq = 100/50/25MHz) Drive Type = C Total load capacitance supported Drive Type = D Possibly 22pF+ depending on host system Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 96...

  • Page 112: Table 11-5. Sdcard Signal Connections

    Near Device/Connector pin. SD connector pin can be used for device end if accessible. One SDCARD_DATx line and one for Near Jetson AGX Xavier and Device pins. SD connector pin can be used for SDCARD_CMD. device end if accessible. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 97...

  • Page 113: Chapter 12. Audio

    Expansion Connector GPIO08 CAN1_STB GPIO / Digital Mic Input Data Bidir (AO DMIC In Data) CMOS – 3.3V Expansion Connector GPIO09 CAN1_EN GPIO / Digital Mic Input Clock Bidir (AO DMIC In Clock) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 98...

  • Page 114: Table 12-2. I2S Interface Mapping

    GPIO functionality, so support both input and output operation (bidirectional). When possible, the following assignments should be used for the I2Sx interfaces. Table 12-2. I2S Interface Mapping Module Pins (SoC Functions) Xavier I/O Block Typical Usage (Usage on NVIDIA Carrier Board) I2S1 (I2S1) AUDIO Audio Codec I2S2 (I2S2) CONN...

  • Page 115: Figure 12-1. Audio Device Connections

    = 1 (SDATA driven on positive edge of SCLK). The value of the capacitor should be chosen to provide a minimum of 2ns hold time for the DAPn_FS edge after the rising edge of DAPn_SCLK. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 100...

  • Page 116: I2S Design Guidelines

    JAXi: No I2S support. GPIO only. I2S1_DOUT (I2S1_SDOUT) I2S Data Output: Connect to Data Input I2S2_DOUT (I2S2_SDOUT) pin of audio device. I2S3_DOUT (I2S4_SDOUT) JAX: GPIO05 (I2S6_SDOUT) JAXi: No I2S support. GPIO05 connected to CAN0_ERR on module. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 101...

  • Page 117: Dmic Design Guidelines

    Type Terminatio Description Function) GPIO09 (DMIC[5 or 3]_CLK) Digital Microphone Clock: Connect to clock pin of DMIC device GPIO08 (DMIC[5 or 3]_DAT) Digital Microphone Data: Connect to data pin of DMIC device Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 102...

  • Page 118: Chapter 13. Miscellaneous Interfaces

    HDMI Connector DP2_AUX_CH_P DP_AUX_CH2_P DisplayPort 2 Aux+ or HDMI DDC SCL Notes: In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 103...

  • Page 119: Table 13-2. I2C Interface Mapping

    Xavier reset is low. PWR_I2C when reset is high. I2C6 DP0_AUX_CH_N/P None I2C7 DP2_AUX_CH_N/P None I2C8 I2C4_CLK/DAT 1KΩ to 1.8V I2C9 I2C5_CLK/DAT 1KΩ to 1.8V VM_I2C_SCK_DAT See I2C5 row Usage on Module description. None Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 104...

  • Page 120: I2C Design Guidelines

    Xavier do not have duplicate addresses. Addresses can be in two forms: 7-bit, with the Read/Write bit removed or 8-bit including the Read/Write bit. Be sure to compare I2C device addresses using the same form (all 7-bit or all 8-bit format). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 105...

  • Page 121: Table 13-3. I2C Interface Signal Routing Requirements

    For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 106...

  • Page 122: Bounce

    In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. JAXi only: SPI2 routed to safety MCU if implemented in design. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 107...

  • Page 123: Spi Design Guidelines

    SPI Design Guidelines The following figures show the SPI topologies. Figure 13-4. SPI Point-Point Topology Module Device Main trunk Figure 13-5. SPI Star Topologies Device #1 Module Branch-A Main trunk Device #2 Branch-B Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 108...

  • Page 124: Figure 13-6. Spi Daisy Topologies

    Note: JAXi only: SPI2 routed to safety MCU if implemented in design Table 13-9. Recommended SPI Observation Test Points for Initial Boards Test Points Recommended Location One for each SPI signal line used Near Jetson AGX Xavier and Device pins. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 109...

  • Page 125: Uart

    In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. The direction indicated for the UART pins is true when used for that function. Otherwise, these pins support GPIO functionality and can support both input and output (bidirectional). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 110...

  • Page 126: Figure 13-7. Jetson Agx Xavier Uart Connections

    SPI2_MISO (UART7_RX) UART[5,2:1]_CTS and SPI2_CS0_N UART Clear to Send: Connect to Peripheral RTS_N pin (UART7_CTS) of device UART[5,2:1]_RTS and SPI2_MOSI UART Request to Send: Connect to Peripheral CTS pin (UART7_RTS) of device Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 111...

  • Page 127: Can

    Jetson AGX Xavier SoC - CAN CAN #0 CAN0_DOUT CAN0_DOUT AO_HV CAN0_DIN CAN0_DIN CAN1_DOUT CAN1_DOUT CAN1_DIN CAN1_DIN B6 1 GPIO06 CAN0_EN GPIO07 CAN0_WAKE CAN #1 GPIO09 CAN1_EN GPIO10 CAN1_WAKE GPIO08 CAN1_STB B6 2 Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 112...

  • Page 128: Table 13-14. Can Interface Signal Routing Requirements

    CAN Enable: Connect to matching pin of device GPIO09 (CAN1_EN) GPIO08 (CAN1_STB) CAN 1 Standby: Connect to matching pin of device GPIO07 (CAN0_WAKE) CAN Wake: Connect to matching pin of device GPIO10 (CAN1_WAKE) Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 113...

  • Page 129: Chapter 14. Fan

    In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. The direction indicated for FANx is associated with their use as Fan PWM/Tach. The pins support GPIO functionality, so support both input and output operation (bidirectional). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 114...

  • Page 130: Figure 14-1. Jetson Agx Xavier Fan Connection Example

    100kΩ pulldown to GND. Fan Pulse Width Modulation: Connect through FET as shown in the Jetson AGX Xavier Fan Connections figure. FAN_TACH 100kohm pullup to Fan Tachometer: Connect to TACH pin on fan VDD_1V8 connector. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 115...

  • Page 131: Chapter 15. Debug And Strapping

    5V from the host system VBUS supply. If the supply on the Xavier system is present and enabled, the VBUS pin should not be connected from the host (special cable with VBUS disconnected). Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 116...

  • Page 132: Jtag And Debug Uart

    Figure 15-2. Simple Debug UART Header Connections VDD_1V8 VDD_3V3 Jetson AGX Xavier Level Shifter Serial Port VCCB VCCA Header 0.1uF 0.1uF UART 3_TX_DEBUG UART3_TX UART 3_RX_DEBUG UART3_RX Level Shifter 0.1uF VCCA VCCB 0.1uF Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 117...

  • Page 133: Jtag

    JTAG_TRST_N Unused Input CMOS – 1.8V mode. Pulled to GND through 100kΩ resistor on module. NVIDIA Debug Select. Pulled to GND through NVDBG_SEL NVDBG_SEL Input 100kΩ resistor on module. NVIDIA JTAG Select. Low for normal Unused – Driven to GND operation or ARM JTAG debug mode.

  • Page 134: Debug Uart

    That strap is used to enter Force Recovery mode (held low during power-on). The other straps mentioned in this section are for use on the module by NVIDIA only. Their state at power-on must not be affected by any connections on the carrier board. The carrier board design should guarantee a high-z on the pins during boot.

  • Page 135: Boundary Scan Test Mode

    Leave Resistors R1 & R2 uninstalled SYS_RESET_N for normal operation. Install both for boundary scan test mode. eMMC R2 - 0Ω PERIPHERAL_RESET_N RESET* 1kΩ VDDIO_AO_1V8 PMIC Devices requiring system reset SYS_RESET_N RST I/O & System Reset Sources Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 120...

  • Page 136: Safety Mcu Jaxi Only

    Open Drain, 1.8V THERM_OUT) THERM* output. 10kΩ pullup to 1.8V on module. Notes: In the Type/Dir column, Output is from Jetson AGX Xavier. Input is to Jetson AGX Xavier. Bidir is for Bidirectional signals. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 121...

  • Page 137: Figure 15-5. Safety Mcu Connections

    SOC_GPIO[09:08] SPI2_CLK SPI2_SCK SPI2_MISO SPI2_MISO SPI2_MOSI SPI2_MOSI Level SPI2_CS0_N SPI2_CS0# Shifter 100kΩ 1.8V GPIO31 SAFE_STATE 1kΩ 1.8V 1kΩ VM_I2C_SCK PWR_I2C_SCL VM_I2C_DAT PWR_I2C_SDA SYS_RESET_N 10kΩ 3.3V Voltage VM_INT_N On-Module Monitors Control PMIC SYS_RESET_N Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 122...

  • Page 138: Chapter 16. Pads

    Jetson AGX Xavier Signal Terminations section of the Design Checklist chapter. Care must be taken on the carrier board design to ensure that any of these pins that connect to Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 123...

  • Page 139: Pad Drive Strength

    +/- 1mA LV_CZ 0.15*VDD 0.85*VDD +/- 2mA 0.15*VDD 0.7*VDD +/- 2mA 0.175*VDD 0.7*VDD +/- 2mA CZ (1.8V mode) 0.25*VDD 0.75*VDD +/- 2mA CZ (3.3V mode) 0.15*VDD 0.75*VDD +/- 2mA LV_CZ 0.25*VDD 0.75*VDD Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 124...

  • Page 140: Chapter 17. Unused Interface Terminations

    (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 125...

  • Page 141: Chapter 18. Design And Bring-Up Checklists

    (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 126...

  • Page 142: Chapter 19. General Layout Guidelines

    Jetson AGX Xavier. Vias can have a strong impact on power distribution and signal noise, so careful planning must take place to ensure designs meet NVIDIA’s via requirements. Trace length and impedance determine signal propagation time and reflections, both of which can greatly improve or reduce the performance of Jetson AGX Xavier.

  • Page 143: Figure 19-1. Via Placement For Good Power Distribution

    Poor Current Flow Resulting from Incorrect Via Placement With insufficient via spacing Incorrect via implementation In general, a dense via population should be avoided and good PCB design principles and analysis should be applied. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 128...

  • Page 144: Connecting Vias

    (see Chapter 21 “Transmission Line Primer”) to determine proper trace characteristics for a signal. All signals on the graphics card maintain different trace guidelines. Refer to the corresponding signal chapter in the design guide to determine the guidelines for the signal. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 129...

  • Page 145: Chapter 20. Stack-Ups

    Critical signals must be adjacent to major and minor reference planes and adhere to proximity constraints with respect to those planes. The recommended NVIDIA stack-ups achieve these requirements for the signal speeds supported by the board.

  • Page 146: Chapter 21. Transmission Line Primer

    Chapter 21. Transmission Line Primer 21.1 Basic Board Level Transmission Line Theory NVIDIA maintains strict guidelines for high-frequency PCB transmission lines to ensure optimal signal integrity for data transmission. This section provides a brief primer into basic board-level transmission line theory. 21.1.1...

  • Page 147: Physical Transmission Line Types

    Stripline Transmission Line 0.67πW 0.8 + Z0: Impedance • W: Trace width (inches) • T: Trace thickness (inches) • Er: Dielectric constant of substrate • H: Distance between signal and reference plane • Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 132...

  • Page 148: Drive Characteristics

    – Z R2 = Load impedance can be lowered with a termination resistor (R ) placed at the end of the  Term transmission line. Reflection is minimized when Z matches Z • Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 133...

  • Page 149: Transmission Lines And Reference Planes

    Crosstalk is caused by the mutual inductance of two parallel traces. • Crosstalk at the second trace is proportional to • The signals need to be properly spaced to minimize crosstalk • Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 134...

  • Page 150: Figure 21-5. Crosstalk On Reference Plane

     Place decoupling capacitors near transition. • Place transition near source or receiver when decoupling capacitors are abundant • (Figure 21-7). Figure 21-7. Power Plane Cuts Example when Decouple Capacitors are abundant Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 135...

  • Page 151: Figure 21-8. Switching Reference Planes

    When the same ground and power reference plane changes to a different layer, a • stitching via is required (Figure 21-9). Figure 21-8. Switching Reference Planes Figure 21-9. Reference Plane Switch Using Via Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 136...

  • Page 152: Chapter 22. Design Guideline Glossary

    Board Trace Spacing and Spacing to other Nets • Minimum distance between two traces. Usually specified in terms of dielectric height which is distance from trace to reference layers. Pair to Pair Spacing • Spacing between differential traces. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 137...
  • Page 153 Placing one cap across two PWR areas near where traces cross area − boundaries provides high-frequency path for return current. Cap value typically 0.1uF and should ideally be within 0.1" of crossing. − Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 138...
  • Page 154 USB SS connector itself. If possible, the antenna or USB SS location can be changed to increase physical isolation. In general, doubling the distance between antenna and noise source, reduces the coupling by around 6 dB. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 139...
  • Page 155 USB SS connectors. The shield must touch the USB SS body in multiple points. The shield track must have number of grounding vias so that any emitted noise from the USB SS connector is swiftly grounded. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 140...
  • Page 156 (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 141...
  • Page 157 NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this document. NVIDIA accepts no liability related to any default, damage, costs, or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this document or (ii) customer product designs.

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