Pcie Design Guidelines; Table 6-9. Pcie Interface Signal Routing Requirements To Gen3 - Nvidia Jetson Xavier NX Design Manual

6.2.1

PCIe Design Guidelines

The following tables provide the PCIe routing guidelines for the PCIe #1 (x1) or PCIe #0 (x4)
interfaces. PCIe #1 supports up to Gen3 and the first table applies. PCIe #0 supports up to
Gen4 and if the design will need to operate at Gen4 speed, the second routing table applies.
Table 6-9. PCIe Interface Signal Routing Requirements to Gen3
Parameter
Specification
Data Rate / UI Period
Configuration / Device Organization
Topology
Termination
Impedance
Trace Impedance differential / Single
Ended
Reference plane
Spacing
Trace Spacing (Stripline/Microstrip)
Pair – Pair
To plane and capacitor pad
To unrelated high-speed signals
Length/Skew
Trace loss budget (for carrier board routing)
Routing direct to device
Routing to PCIe/M.2 connector
Breakout region (Max Length)
Max trace length (delay)
Direct to device on carrier board
Stripline
Microstrip
Routed to PCIe or M.2 connector
Stripline
Microstrip
Max PCB via distance from the BGA
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of Vias
PTH Vias
Micro-Vias
Max Via stub length
Routing signals over antipads
NVIDIA Jetson Xavier NX
Requirement Units
8.0 / 125 Gbps / ps
1 Load
Point-point
50 Ω
85 / 50 Ω
GND
3x / 4x Dielectric
3x / 4x
3x / 4x
-11.5 dB
-7.5
41.9 ps
15.3 (2680) in (ps)
14.4 (2160)
10 (1750)
9.4 (1400)
41.9 ps
0.075 (0.5) mm (ps)
0.075 (0.5) mm (ps)
41.9 ps
Place GND vias as symmetrically as possible to data pair vias. GND via distance
should be placed less than 1x the diff pair via pitch
2 for TX traces and 2 for RX trace
No requirement
0.4 mm
Not allowed
USB and PCIe
Notes
4.0GHz, half-rate architecture
differential
Unidirectional,
To GND Single Ended for P & N
±15%. See Note 1
TX and RX should not be routed on the
same layer. See Note 2.
@ 4GHz (See Figure 6-3),
Loss: GEN3 budget – module – end
device – safety margin (-22dB + 3.5dB +
4dB + 3dB)
Loss: GEN3 budget – module – end
device – safety margin (-22dB + 3.5dB +
8dB + 3dB)
Minimum width and spacing. 4x or
wider dielectric height spacing is
preferred
Mid-loss PCB of 0.8dB/in (Microstrip) or
0.75dB/in (Stripline) is used. Also,
175ps/in for Stripline routing and
150ps/in for Microstrip.
Max distance from BGA ball to first PCB
via.
Do trace length matching before hitting
discontinuities. See notes 3 and 4.
See notes 3 and 4.
Longer via stubs would require review
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