Figure 7-10. Pcie Endpoint Connections Example - Nvidia Jetson Orin NX Design Manual

Figure 7-10 shows the x4 interface configured as Endpoint for the PCIe Endpoint connections.
Figure 7-10. PCIe Endpoint Connections Example
SoC - PCIe
UPHY0
HS_UPHY0_L7_TX_N/P
HS_UPHY0_L7_RX_N/P
HS_UPHY0_L6_TX_N/P
HS_UPHY0_L6_RX_N/P
HS_UPHY0_L5_TX_N/P
HS_UPHY0_L5_RX_N/P
HS_UPHY0_L4_TX_N/P
HS_UPHY0_L4_RX_N/P
HS_UPHY0_REFCLK2_N/P
SF_PCIE4_CLK_N/P
See Note 1
PEX
GP185_PCIE_WAKE_N
Ctrl
GP183_PCIE4_CLKREQ_N
GP184_PCIE4_RST_N
Notes:
1. For Endpoint operation, the mux should be set to output the HS_UPHY2_REFCLK2 signals.
SoC GP21 which is used for the mux select should be set high.
2. AC capacitors required on RX lines on carrier board if connected directly to device. They
should not be on the carrier board if connected to PCIe connector, M.2 Key M, etc. In those
cases, the AC caps are on the board connected to those connectors.
3. See design guidelines for correct AC capacitor values.
4. Isolation circuitry is required on the PCIe control signals when Jetson Orin NX is configured
as Endpoint. These isolate the lines from the on-module pull-ups as well as ensure the
Endpoint and Root Port devices do not have their pads driven high before power is applied.
5. The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification
"REFCLK DC Specifications and AC Timing Requirements." The clocks are HCSL compatible.
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Jetson
PCIE0_TX3_N/P
PCIE0_RX3_N/P
PCIE0_TX2_N/P
PCIE0_RX2_N/P
PCIE0_TX1_N/P
PCIE0_RX1_N/P
PCIE0_TX0_N/P
PCIE0_RX0_N/P
PCIE0_CLK_N/P
Mux
GP21
SEL
3.3V
PCIE_WAKE*
PCIE0_CLKREQ*
HS_UPHY0 _REFCLK2/
GP21
SF_PCIE4_CLK Mux Control
154/156
PCIe 0 Lane 3
155/157
148/150
PCIe 0 Lane 2
149/151
140/142
PCIe 0 Lane 1
137/139
134/136
PCIe 0 Lane 0
131/133
160/162
OD
179
180 OD
PCIE0_RST*
181
See Note 4
OD
USB and PCIe
See Note 2
PCIe 0 (Ctrl #4) –
PCIe x4 Endpoint
3V3_RP
3V3_EP
OD
PCIe 0 (Ctrl
#10) – PCIe
x4 Endpoint
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