Nvidia Jetson Xavier NX Design Manual page 45

Module Pin Name
PCIE0_CLKREQ*
PCIE0_RST*
PCIe Interface 1 (x1 – Controller #4)
PCIE1_TX0_N/P DIFF OUT
PCIE1_RX0_N/P DIFF IN
PCIE1_CLK_N/P DIFF OUT
PCIE1_CLKREQ* I/O (Root Port)
I (Endpoint)
PCIE1_RST* O (Root Port)
I (Endpoint)
Common
PCIE_WAKE*
NVIDIA Jetson Xavier NX
Type Termination
I/O 47kΩ pull-up to
VDD_3V3_SYS on
module
O 4.7kΩ pull-up to
VDD_3V3_SYS on
module
Series 0.22uF
Capacitor
Series 0.22uF
capacitors near Jetson
Xavier NX pins or
device if device on
main PCB.
47kΩ pull-up to
VDD_3V3_SYS on
module
4.7kΩ pull-up to
VDD_3V3_SYS on
module
I 100kΩ pull-up to
VDD_3V3_SYS on
module
Description
PCIe Clock Request for PCIE0_CLK: Connect to CLKREQ pins on
device/connector(s). If the module is configured as an Endpoint,
include open-drain buffers between the clock request pin on the
module and the device/connector. One buffer should have the
output to the module and be powered by the 3.3V rail on the
module. The other buffer should have the output pointing at the
connector/device and be powered by the 3.3V rail at the
connector/device. These buffers isolate the on-module pull-up
resistors as well as ensures the pins on both the Root Port and
Endpoint sides will not be driven high before the associated power
is enabled.
PCIe Reset: Connect to PERST pins on device/connector(s). If the
module is configured as an Endpoint, include an open-drain buffer
between the reset pin on the module and the device/connector
powered by the 3.3V rail at the connector/device. The buffer should
have the output toward the module. This isolates the on-module
pull-up resistor as well as ensures this signal will not be
pulled/driven high before the module is powered on.
Differential Transmit Data Pair: Connect to TX_N/P pins of PCIe
connector or RX_N/P pin of PCIe device through AC cap according
to supported configuration.
Differential Receive Data Pair: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap according
to supported configuration.
Differential Reference Clock Output: Connect to REFCLK_N/P
pins of PCIe device/connector
PCIe Clock Request for PCIE1_CLK: Connect to CLKREQ pins on
device/connector(s)
PCIe Reset: Connect to PERST pins on device/connector(s)
PCIe Wake: Connect to WAKE pins on device or connector. If the
module is configured as an Endpoint, include an open-drain buffer
between the wake pin on the module and the device/connector
powered by the 3.3V rail at the connector/device. The buffer should
have the output toward the connector/device. This isolates the on-
module pull-up resistors as well as ensures this signal will not be
pulled/driven high before the Root Port is powered on.
USB and PCIe
DG-09693-001_v1.7 | 34