Figure 6-9. Pcie Root Port Connections Example - Nvidia Jetson Xavier NX Design Manual

Figure 6-9. PCIe Root Port Connections Example
SoC - PCIe
NVHS
NVHS_TX3_N
NVHS_TX3_P
NVHS_RX3_N
NVHS_RX3_P
NVHS_TX2_N
NVHS_TX2_P
NVHS_RX2_N
NVHS_RX2_P
NVHS_TX1_N
NVHS_TX1_P
NVHS_RX1_N
NVHS_RX1_P
NVHS_TX0_N
NVHS_TX0_P
NVHS_RX0_N
NVHS_RX0_P
NVHS0_REFCLK_N
NVHS0_REFCLK_P
PEX
PEX_CLK5_N
PEX_CLK5_P
See Note 1
PEX_TX11_N
PEX_TX11_P
PEX_RX11_N
PEX_RX11_P
PEX_CLK4_N
PEX_CLK4_P
PEX
PEX_L4_CLKREQ_N
PEX_L4_RST_N
Control
PEX_WAKE_N
PEX_L5_CLKREQ_N
PEX_L5_RST_N
AO_HV
CAN0_EN
Notes:
1. For Root Port operation, the mux should be set to output the PEX_CLK5 signals. CAN0_EN
which is used for the mux select should be set low.
2. AC Capacitors required on RX lines on carrier board if connected directly to device. They
should not be on the carrier board if connected to PCIe connector, M.2 Key M, etc. In those
cases, the AC caps are on the board connected to those connectors.
3. See design guidelines for correct AC capacitor values.
4. The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification
"REFCLK DC Specifications and AC Timing Requirements." The clocks are HCSL compatible.
Figure 6-10 shows the x4 interface configured as Endpoint for the PCIe Endpoint connections.
NVIDIA Jetson Xavier NX
Jetson
PCIE0_TX3_N
PCIE0_TX3_P
PCIE0_RX3_N
PCIE0_RX3_P
PCIE0_TX2_N
PCIE0_TX2_P
PCIE0_RX2_N
PCIE0_RX2_P
PCIE0_TX1_N
PCIE0_TX1_P
PCIE0_RX1_N
PCIE0_RX1_P
PCIE0_TX0_N
PCIE0_TX0_P
PCIE0_RX0_N
PCIE0_RX0_P
PCIE0_CLK_N
PCIE0_CLK_P
Mux
CAN0_EN
SEL
PCIE1_TX0_N
PCIE1_TX0_P
PCIE1_RX0_N
PCIE1_RX0_P
PCIE1_CLK_N
PCIE1_CLK_P
3.3V
PCIE1_CLKREQ*
PCIE1_RST*
PCIE_WAKE*
PCIE0_CLKREQ*
PCIE0_RST*
NVHS0_REFCLK/PEX_CLK5
Mux Control
See Note 2
154
156
PCIe 0 Lane 3
155
157
148
150
PCIe 0 Lane 2
149
151
140
142
PCIe 0 Lane 1
137
139
134
136
PCIe 0 Lane 0
131
133
160
162
172
174
PCIe 1 Lane 0
167
169
173
175
182
183
Shared wake pin
179
180
181
USB and PCIe
PCIe 0 (Ctrl #5) –
PCIe x4 conn/device
(i.e. M.2 Key M)
PCIe 0 (Ctrl #4) –
PCIe x1 conn/device
(i.e. M.2 Key E)
PCIe 1 (Ctrl #4) –
PCIe x1 conn/device
(i.e. M.2 Key E)
PCIe 0 (Ctrl #5) –
PCIe x4 conn/device
(i.e. M.2 Key M)
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