Uart; Table 12-6. Spi Signal Connections; Table 12-7. Uart Pin Descriptions - Nvidia Jetson Xavier NX Design Manual

Table 12-6. SPI Signal Connections
Module Pin Names (Function)
SPI[1:0]_CLK
SPI[1:0]_MOSI
SPI[1:0]_MISO
SPI[1:0]_CS[1:0]*
12.3

UART

The Jetson Xavier NX brings three UARTs out to the main connector. See Figure 12-5 for
typical assignments of the three available UARTs.

Table 12-7. UART Pin Descriptions

Module Pin
Pin # Xavier Signal
Name
99 UART0_TXD UART2_TX
101 UART0_RXD UART2_RX
103 UART0_RTS* UART2_RTS
105 UART0_CTS* UART2_CTS
203 UART1_TXD UART1_TX
205 UART1_RXD UART1_RX
207 UART1_RTS* UART1_RTS
209 UART1_CTS* UART1_CTS
236 UART2_TXD UART3_TX
238 UART2_RXD UART3_RX
Notes:
1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals.
2. The direction indicated for the UART pins except for is true when used for that function. Otherwise, these pins support GPIO
functionality and most can support both input and output (bidirectional) functionality. The exception is UART0_TXD, UART0_RTS*
and UART1_TXD. These have output-only buffers on the module to keep them from being affected by connected devices during
boot as they are associated with SoC strapping pins.
NVIDIA Jetson Xavier NX
Type Termination Description
I/O SPI Clock.: Connect to peripheral CLK pin(s)
I/O SPI Data Output: Connect to target peripheral MOSI pin(s)
I/O SPI Data Input: Connect to target peripheral MISO pin(s)
I/O SPI Chip Selects.: Connect one CSx* pin per SPI interface to
each target peripheral CS pin on the interface
Usage/Description
UART 0 Transmit
UART 0 Receive
UART 0 Request to Send
UART 0 Clear to Send
UART 1 Transmit
UART 1 Receive
UART 1 Request to Send
UART 1 Clear to Send
UART 2 Transmit.
UART 2 Receive
Miscellaneous Interfaces
Recommended Directio
Pin Type
Usage n
Output
Input
UART general
(i.e. M.2 Key E)
Output
Input
Output
CMOS –
1.8V
Input
UART general
Output
Input
Output
Debug UART
Input
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