Figure 7-5. Pcie Endpoint Connection Example - Nvidia Jetson AGX Xavier Series Design Manual

Figure 7-5. PCIe Endpoint Connection Example
Jetson AGX Xavier
SoC - PCIe
NVHS0_RX0_N/P
NVHS
NVHS0_TX0_N/P
NVHS0_RX1_N/P
NVHS0_TX1_N/P
NVHS0_RX2_N/P
NVHS0_TX2_N/P
NVHS0_RX3_N/P
NVHS0_TX3_N/P
NVHS0_RX4_N/P
NVHS0_TX4_N/P
NVHS0_RX5_N/P
NVHS0_TX5_N/P
NVHS0_RX6_N/P
NVHS0_TX6_N/P
NVHS0_RX7_N/P
NVHS0_TX7_N/P
PEX_CLK5_N/P
NVHS0_REFCLK_N/P
PEX
Control
PEX_L5_CLKREQ_N
PEX_L5_RST_N
PEX_WAKE_N
Note: See "Notes" under Figure 7-4.
Jetson AGX Xavier Series Product
NVHS0_SLVS_RX0_N/P
D25/D24
NVHS0_TX0_N/P
H25/H24
NVHS0_SLVS_RX1_N/P
B2 4/B25
NVHS0_TX1_N/P
K24/K25
NVHS0_SLVS_RX2_N/P
C26/C27
NVHS0_TX2_N/P
G26/G27
NVHS0_SLVS_RX3_N/P
A27/A26
_
NVHS0_TX3_N/P
J27/J26
NVHS0_SLVS_RX4_N/P
D29/D28
NVHS0_TX4_N/P
H29/H28
NVHS0_SLVS_RX5_N/P
B2 8/B29
NVHS0_TX5_N/P
K28/K29
NVHS0_SLVS_RX6_N/P
C30/C31
NVHS0_TX6_N/P
G30/G31
NVHS0_SLVS_RX7_N/P
A31/A30
NVHS0_TX7_N/P
J31/J30
PEX_CLK5_N/P
F25/F24
NVHS0_SLVS_REFCLK_N/P
E31/E30
VDDIO_AO_3V3
PEX_L5_CLKREQ_N
PEX_L5_RST_N
PEX_WAKE_N
0.22uF Lane 0
0.22uF Lane 1
0.22uF Lane 2
0.22uF Lane 3
PCIe x8 (I/F C5)
0.22uF Lane 4
0.22uF Lane 5
0.22uF Lane 6
0.22uF Lane 7
Not used when module C5
I/F is used as Endpoint
100MHz clock input required to support
Endpoint on PCIe x8 (NVHS pins – C5)
Control for PCIe I/F C5
C8
(PCIe x16 Connector on Carrier Board)
H10
Not used by PCIe I/F configured as Endpoint.
A8
Used for Root Port Wake only.
USB, PCIe, and UFS
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