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Nvidia Jetson Xavier NX Design Manual

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NVIDIA Jetson Xavier NX
Design Guide
DG-09693-001_v1.7
|
November 2022

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Summary of Contents for Nvidia Jetson Xavier NX

  • Page 1 NVIDIA Jetson Xavier NX Design Guide DG-09693-001_v1.7 November 2022...
  • Page 2 Updated Table 13-1 • Updated Table 13-2 • 0.92 March 23, 2020 Removed PMIC part # from Figure 2-1 • Added new chapter on module connector (Chapter 3) • Added note to Section 5.1 “USB” NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | ii...
  • Page 3 Added Gen2 specific requirements to ESD • Updated Table 6-5 with max trace lengths (more relaxed) and PTH vias (more restrictive) • Updated Table 7-4 with the following: Removed max loading spec NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | iii...
  • Page 4 Added section on test points for high-speed interfaces (Section 17.6 • Updated pin description attachment • September 20, 2021 Removed WiFi/BT/Modem row in Table 2-1”Jetson Xavier NX Interfaces” • Updated Section 5.1 “Power Supply and Sequencing” text • Updated Figure 5-2 “Power Up Sequence (No Power Button – Auto Power On)”...
  • Page 5 Figure 11-1: Corrected I2C pull-up voltage in note 2 under figure. • Table 13-1: Removed SYS_RESET* • Table 13-2: Corrected pull-up value on-module for PCIE_WAKE* • Section 18.2/18.3/18.4: Updated text to use mm instead of in/mils NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | v...

  • Page 6: Table Of Contents

    Chapter 1. Introduction ....................... 1 References ........................1 Abbreviations and Definitions ..................1 Chapter 2. Jetson Xavier NX ....................3 Chapter 3. Developer Kit Feature Considerations .............. 7 Button Power MCU ......................7 USB SuperSpeed Hub ...................... 8 Power over Ethernet ......................8 TI TXB0108 Level Shifters ....................
  • Page 7 USB 3.2 and Wireless Coexistence ..............82 15.1 Mitigation Techniques ....................82 Chapter 16. Design and Bring-Up Checklists ..............84 Chapter 17. Jetson Xavier NX Pin Descriptions ..............85 Chapter 18. General Routing Guidelines ................86 18.1 Signal Name Conventions ....................86 18.2 Routing Guideline Format ....................
  • Page 8 List of Figures Figure 2-1. Jetson Xavier NX Block Diagram ................4 Figure 4-1. Jetson Xavier NX Module Installed in SODIMM Connector ........9 Figure 4-2. Module to Connector Assembly Diagram ............10 Figure 5-1. System Power and Control Block Diagram ............13 Figure 5-2.
  • Page 9 Figure 12-7. Fan Connections ....................75 Figure 12-8. Debug UART Connections ..................76 Figure 18-1. General PCB Routing Guidelines ................ 88 Figure 18-2. Common Mode Choke ..................89 Figure 18-3. Serpentine ......................90 NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | ix...
  • Page 10 Abbreviations and Definitions ................2 Table 2-1. Jetson Xavier NX Interfaces ................... 3 Table 2-2. Jetson Xavier NX Connector (260-Pin SO-DIMM) Pin Out Matrix ......5 Table 5-1. Power and System Pin Description ..............11 Table 6-1. USB 2.0 Pin Description ..................17 Table 6-2.
  • Page 11 Pins with External Pull-ups to Supply on before SYS_RESET* Inactive ... 80 Table 14-1. Unused MPIO Pins and Pin Group ............... 81 Table 18-1. Signal Type Codes ....................86 Table 18-2. Common High-Speed Interface Requirements ..........89 NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | xi...

  • Page 12: Chapter 1. Introduction

    Jetson Xavier NX Module Pinmux  Jetson Xavier NX Thermal Design Guide  Jetson Xavier NX SCL (Supported Component List)  Abbreviations and Definitions Table 1-1 lists the abbreviations that may be used throughout this design and guide and their definitions.

  • Page 13: Table 1-1. Abbreviations And Definitions

    8P8C modular connector used in Ethernet and other data links Real Time Clock SD Card Secure Digital Card SDIO Secure Digital I/O Interface Single-Ended Serial Peripheral Interface TMDS Transition-Minimized Differential Signaling UART Universal Asynchronous Receiver-Transmitter Universal Serial Bus NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 2...

  • Page 14: Chapter 2. Jetson Xavier Nx

    Chapter 2. Jetson Xavier NX The Jetson Xavier NX resides at the center of the embedded system solution and includes: Power (PMIC/Regulators, etc.)  DRAM (8 GB, 128-bit LPDDR4x)  eMMC (16 GB)  Gigabit Ethernet Controller  Power Monitor ...

  • Page 15: Figure 2-1. Jetson Xavier Nx Block Diagram

    Jetson Xavier NX Figure 2-1. Jetson Xavier NX Block Diagram Jetson Xavier NX Power LPDDR4x VDD_IN USB 2.0 3x Subsystem PMIC Gigabit GBE_MDI USB 3.1 1x Ethernet CPU/GPU & Core Regs QSPI N OR SD CARD/SDIO PCIe x1 + x4 Power &...

  • Page 16: Table 2-2. Jetson Xavier Nx Connector (260-Pin So-Dimm) Pin Out Matrix

    Jetson Xavier NX Table 2-2. Jetson Xavier NX Connector (260-Pin SO-DIMM) Pin Out Matrix Module Signal Name Pin # Pin # Module Signal Name Module Signal Name Pin # Pin # Module Signal Name PCIE0_RX0_P PCIE0_TX0_N CSI1_D0_N CSI0_D0_N PCIE0_TX0_P CSI1_D0_P...
  • Page 17 SPI1_CS0* SYS_RESET* SLEEP/WAKE* USB0_D_P SPI1_CS1* CAM0_PWDN USB1_D_N CAM0_MCLK USB1_D_P GPIO01 CAM1_PWDN USB2_D_N CAM1_MCLK VDD_IN VDD_IN USB2_D_P GPIO02 VDD_IN VDD_IN GPIO03 VDD_IN VDD_IN GPIO04 GPIO05 VDD_IN VDD_IN GPIO06 VDD_IN VDD_IN PCIE0_RX0_N Legend Ground Power NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 6...

  • Page 18: Chapter 3. Developer Kit Feature Considerations

    Chapter 3. Developer Kit Feature Considerations The Jetson Xavier NX Developer Kit Carrier Board design files are provided as a reference design. This chapter describes details necessary for designers to know to replicate certain features if desired. In addition, aspects of the design that are specific to the NVIDIA Developer Kit usage but not useful or supported on a custom carrier board are also identified.

  • Page 19: Usb Superspeed Hub

    Features Not to be Implemented The Jetson Xavier NX Developer Kit carrier board features that should not be copied as they are not required or useful for a custom carrier board design. The ID EEPROM (P3509 - U17) is a feature that is used for NVIDIA internal purposes, but not useful on a custom design.

  • Page 20: Chapter 4. Modular Connector

    Jetson Xavier NX modules connect to the carrier board using a 260-pin SODIMM connector. The mating connector used on the developer kit carrier board is listed in the Jetson Xavier NX SCL (Supported Components List). This connector is a DDR4 SODIMM, 260-pin, right-angle, standard key type.

  • Page 21: Module Installation And Removal

    Modular Connector Module Installation and Removal To install the Jetson Xavier NX module correctly, follow the sequence and mounting hardware instructions: Here are some suggested assembly guidelines. Assemble any required thermal solution on the module. Install the module Start with baseboard that has suitable standoff to match SODIMM connector height.

  • Page 22: Chapter 5. Power

    VDD_IN Xavier NX Data Sheet for supply tolerance and maximum current). CAUTION: Jetson Xavier NX is not hot-pluggable. Before installing or removing the module, the main power supply (to VDD_IN pins) must be disconnected and adequate time allowed for the various power rails to fully discharge.

  • Page 23: Power Supply And Sequencing

    1.8V Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. The directions for FORCE_RECOVERY* and SLEEP/WAKE* signals are true when used for those functions. Otherwise as GPIOs, the direction is bidirectional.

  • Page 24: Figure 5-1. System Power And Control Block Diagram

    SYS_RESET* Power POWER_EN Logic SHUTDOWN_REQ* Note: Designs which implement an eFUSE or current limiting device on the input power rail of the module should select a part that DOES NOT limit reverse current. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 13...

  • Page 25: Figure 5-2. Power Up Sequence (No Power Button - Auto Power On)

    Power Button POWER_EN ~14ms SYS_RESET* Carrier Board Supplies Note: 1. SHUTDOWN_REQ* is not driven during power up. The signal is pulled to VDD_IN. 2. SYS_RESET* is driven by the PMIC during power up. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 14...

  • Page 26: Figure 5-4. Power Down (Initiated By Shutdown_Req* Assertion)

    Power Down (Initiated by POWER_EN De-assertion) VDD_IN SHUTDOWN_REQ* POWER_EN Module Power SYS_RESET* Carrier Board Supplies 3.3V: T < 1.5mS 1.8V: T < 4mS Note: SYS_RESET* is driven by the PMIC during power down. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 15...

  • Page 27: Figure 5-6. Power Down (Sudden Power Loss)

    Power Down (Sudden Power Loss) VDD_IN 3.0V T > 10mS SHUTDOWN_REQ* POWER_EN Note: SHUTDOWN_REQ* must always be serviced by the carrier board to toggle POWER_EN from high to low, even in cases of sudden power loss. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 16...

  • Page 28: Chapter 6. Usb And Pcie

    USB 2.0, Port 2 Data conn/device/hub Bidir USB PHY USB2_D_P USB2_DP (i.e. M.2 Key E) Note: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 17...

  • Page 29: Table 6-2. Usb 3.2 And Pcie Pin Description

    Root Port). When CAN0_EN is Bidir PCIe PHY PEX_CLK5P or high, NVHS0_REFCLK is selected (reference PCIE0_CLK_P NVHS0_REFCLK_ clock input when Jetson Xavier NX is an Endpoint). PCIE1_RX0_N PEX_RX11_N PCIe #1 Receive 0 (PCIe Ctrl #4 Lane 0) Input PCIe PHY...

  • Page 30: Usb

    Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. The direction shown in this table for PEX_L4_RST* and PCIE_WAKE* signals is true when used for those PCIe functions.

  • Page 31: Figure 6-1. Usb 3.2 Micro B Usb Device And Recovery Connection Example

    TX_p TPD4E 05U06 Notes: 1. AC capacitors should be located close to either the USB connector, or the Jetson Xavier NX pins. 2. Connector used must be USB Implementers Forum certified if USB 3.2 is implemented. 3. The load switch supplying VBUS should have over current protection. In Figure 6-2 this is supported by routing the over current (OC) pin of the load switch to the GPIO00 (USB_VBUS_EN0) which is bidirectional and can be used to detect an over current condition.

  • Page 32: Usb 2.0 Design Guidelines

    GEN1 (Micro AB) -1[*] dB @ 2.5GHz The resonance dip could be caused by a Resonance Dip Frequency > 8 via stub for layer transition or trace stub for co-layout. Time-domain Reflectometer (TDR) Dip NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 21...
  • Page 33 Not limited as long as total channel loss meets IL spec Max Via Stub Length long via stub requires review (IL and resonance dip check) Additional Component Placement Order Chip ̶ AC capacitor (TX only) ̶ common mode choke ̶ ESD ̶ Connector NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 22...

  • Page 34: Figure 6-3. Il/Next Plot (Gen1)

    Connector used must be USB-IF certified General: See Chapter 18 for guidelines related to serpentine routing, routing over voids and noise coupling The following figures show the USB 3.2. Interface signal routing requirements. Figure 6-3. IL/NEXT Plot (GEN1) NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 23...

  • Page 35: Figure 6-4. Il/Next Plot (Gen2)

    USB and PCIe Figure 6-4. IL/NEXT Plot (GEN2) Figure 6-5. Via Topology Figure 6-6. Component Order NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 24...

  • Page 36: Common Usb Routing Guidelines

    If used, 90Ω common-mode chokes USB Differential Data Pair: Connect close to connector. ESD Protection to USB connector, Mini-Card socket, USB[2:0]_D_N between choke and connector on each hub or another device on the PCB. line to GND NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 25...

  • Page 37: Pcie

    PCIe Jetson Xavier NX brings two PCIe interfaces to the module pins for up to 5 total lanes (1 x4 + 1 x1) for use on the carrier board. The PCIe x4 interface operates up to Gen4 speed and supports both Root Port and Endpoint operation.

  • Page 38: Figure 6-9. Pcie Root Port Connections Example

    4. The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification “REFCLK DC Specifications and AC Timing Requirements.” The clocks are HCSL compatible. Figure 6-10 shows the x4 interface configured as Endpoint for the PCIe Endpoint connections. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 27...

  • Page 39: Figure 6-10. Pcie Endpoint Connections Example

    Notes: 1. For Endpoint operation, the mux should be set to input the reference clock from the PCIe Root Port device to the Jetson Xavier NX NVHS0_REFCLK pins. CAN0_EN which is used for the mux select should be set high.

  • Page 40: Pcie Design Guidelines

    Max # of Vias PTH Vias 2 for TX traces and 2 for RX trace Micro-Vias No requirement Max Via stub length Longer via stubs would require review Routing signals over antipads Not allowed NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 29...

  • Page 41: Figure 6-11. Insertion Loss S-Parameter Plot (Sdd21)

    4. The average of the differential signals is used for length matching. 5. Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion. Figure 6-11. Insertion Loss S-Parameter Plot (SDD21) NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 30...

  • Page 42: Figure 6-12. Insertion Loss S-Parameter Plot (Sdd11)

    USB and PCIe Figure 6-12. Insertion Loss S-Parameter Plot (SDD11) Figure 6-13. AC Cap Voiding Figure 6-14. Connector Voiding NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 31...

  • Page 43: Table 6-10. Pcie Gen4 Interface Signal Routing Requirements

    1x the diff pair via pitch Max # of Vias Use micro via or back drilled via - no via stub allowed. Max Via stub length Not Allowed AC Cap NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 32...

  • Page 44: Figure 6-15. Example Zig-Zag Routing

    DIFF IN Connect to REFCLK_N/P pins of PCIe device/connector. For Root (Endpoint) Port operation, set the mux to select PEX_CLK5 (CAN0_EN = 0). For Endpoint, set the mux to select NVHS0_REFCLK (CAN_EN = NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 33...
  • Page 45 3.3V rail at the connector/device. The buffer should have the output toward the connector/device. This isolates the on- module pull-up resistors as well as ensures this signal will not be pulled/driven high before the Root Port is powered on. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 34...

  • Page 46: Chapter 7. Gigabit Ethernet

    GbE Transformer Data 2 GBE_MDI2_P − GBE_MDI3_N − GbE Transformer Data 3 GBE_MDI3_P − Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 35...

  • Page 47: Figure 7-1. Ethernet Connections

    GBE_MDI3_N MD3- 0.05Ω POE_VC1 POE_VC2 0.05Ω POE_VC3 Place 0.05Ω resistors & 0.05Ω 22nF POE_VC4 capacitor around each chassis GND shape 100pF 0.05Ω 75Ω each 1000pF 0.05Ω 0.05Ω VDD_3V3_SYS 0.1uF 110Ω GBE_LED_LINK 110Ω GBE_LED_ACT NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 36...

  • Page 48: Table 7-2. Ethernet Mdi Interface Signal Routing Requirements

    Gigabit Ethernet Link LED: Connect to green LED cathode on RJ45 resistor connector. Anode connected to VDD_3V3_SYS GBE_LED_ACT 110Ω (minimum) series Gigabit Ethernet Activity LED: Connect to yellow LED cathode on resistor RJ45 connector. Anode connected to VDD_3V3_SYS NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 37...

  • Page 49: Chapter 8. Display

    Chapter 8. Display Jetson Xavier NX designs can select from several display options including VESA Embedded ® DisplayPort (eDP) for embedded displays, and HDMI or DisplayPort (DP) for external ® ™ displays. The two display interfaces can be run simultaneously.

  • Page 50: Table 8-2. Dp And Hdmi Pin Mapping

    1.8V Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. The direction shown in this table for DP_AUX_CH[1:0]_HPD is true when used for Hot-plug Detect. Otherwise, if used as GPIOs, the direction is bidirectional.

  • Page 51: Edp And Dp

    TPD4E 05U06 Notes: 1. Level shifter required on DP0_HPD to avoid the pin from being driven when Jetson Xavier NX is off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the display). The reference design uses a BJT level shifter and a resistor divider is needed. See the reference design if a similar approach will be used.

  • Page 52: Edp And Dp Routing Guidelines

    @ 2.7GHz dB @ 2.7GHz Impedance Trace impedance Diff pair Ω (±15%) 100Ω is the spec. target. 85Ω is preferable as it can provide better trace loss characteristic performance. See Note 1. Reference plane NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 41...
  • Page 53 4.0GHz Max PCB via dist. from connector RBR/HBR No requirement mm (in) HBR2/HBR3 7.63 (0.3) Max trace length/delay from Jetson Xavier NX TX to connector (Up to HBR3) Stripline 100 (700) mm (ps) 175ps/inch assumption for stripline, Microstrip 150ps/inch for microstrip.

  • Page 54: Figure 8-3. S-Parameter (Up To Hbr2)

    4. The average of the differential signals is used for length matching. The following figures show the eDP and DP interface signal routing requirements. Figure 8-3. S-Parameter (up to HBR2) NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 43...

  • Page 55: Figure 8-4. S-Parameter (Up To Hbr3)

    Display Figure 8-4. S-Parameter (up to HBR3) Figure 8-5. Via Topology #1 Figure 8-6. Via Topology #2 NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 44...

  • Page 56: Hdmi

    Hot Plug Detect: Connect to HPD DP/eDP connector side) and ESD to GND.. pin on display connector through level shifter. HDMI A standard DP 1.2a or HDMI V2.0 interface is supported. See Figure 8-7 for more details. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 45...

  • Page 57: Figure 8-7. Hdmi Connection Example

    3. The DP1_TXx pads are native DP pads and require series AC capacitors (ACCAP) and pull-downs (RPD) to be HDMI compliant. The 499Ω, 1% pull-downs must be disabled when Jetson Xavier NX is off or in sleep mode to meet the HDMI VOFF requirement. The enable to the FET, enables the pull-downs when the HDMI interface is to be used.

  • Page 58: Figure 8-8. Hdmi Clk And Data Topology

    3GHz summation of the individual NEXT effects <= -40 dB at 6GHz on each pair by the other pairs IL/FEXT plot: See HDMI Guideline TDR plot: See Figure 8-10 Figure 8-9 Impedance NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 47...
  • Page 59 50ohm SE traces on PCB top or bottom. Max distance from R to main trace (seg B) Max distance from AC cap to RPD stubbing point (seg A) Max distance between ESD and signal via Add-on Components NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 48...
  • Page 60 Trace at Component Region Value Ω ± 10% Location At component region (Microstrip) Trace entering the SMT pad One 45° See Figure 8-18 Trace between components Uncoupled structure See Figure 8-19 HDMI connector NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 49...

  • Page 61: Figure 8-9. Il/Fext Plot

    4. If routing includes a flex or 2nd PCB, the max trace delay and skew calculations must include all the PCBs/flex routing. Solutions with flex/2nd PCB may not achieve maximum frequency operation. The following figures show the HDMI interface signal routing requirements. Figure 8-9. IL/FEXT Plot Figure 8-10. TDR Plot NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 50...

  • Page 62: Figure 8-11. Hdmi Via Topology

    Display Figure 8-11. HDMI Via Topology Figure 8-12. Add-On Components – Top Figure 8-13. Add-on Components – Bottom Figure 8-14. AC Cap Void NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 51...

  • Page 63: Figure 8-15. Rpd/Choke, Fet Placement

    Display Figure 8-15. RPD/Choke, FET Placement Figure 8-16. ESD Footprint Figure 8-17. ESD Void Figure 8-18. SMT Pad Trace Entering NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 52...

  • Page 64: Figure 8-19. Smt Pad Trace Between

    Adequate decoupling (0.1uF and 10uF HDMI 5V supply to connector: Connect to recommended) on supply near connector and ESD +5V on HDMI connector. to GND. Note: Any ESD and/or EMI solutions must support targeted modes (frequencies). NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 53...

  • Page 65: Chapter 9. Mipi Csi Video Input

    Chapter 9. MIPI CSI Video Input Jetson Xavier NX brings fourteen MIPI CSI lanes to the connector. Up to three quad-lane camera streams plus one dual-lane stream or up to six dual-lane camera streams are supported. Each data lane has a peak bandwidth of up to 2.5 Gbps. The following maximum...
  • Page 66 DSI_D0_P CSI_G_D0_P DSI_D1_N CSI_G_D1_N Camera, CSI 5 Data 1 DSI_D1_P CSI_G_D1_P Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 55...

  • Page 67: Figure 9-1. 4 Lane Csi Camera Connection Example

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction shown in this table for CAM[1:0]_MCLK and CAM[1:0]_PWDN is true when used for those functions. These pins are GPIOs and can support input or output (bidirectional).

  • Page 68: Table 9-3. Csi Configurations

    3 of 3 √ √ cameras Notes: 1. CSI 4 can be used as a x1, x2, or x4 CSI interface. 2. Each 2-lane options shown can also be used for one single lane camera. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 57...

  • Page 69: Figure 9-2. Csi Connection Options

    CSI4_D0_P CSI_E_D0_P (2-Lane) Camera 3 CSI4_D1_N CSI_E_D1_N (4-Lane) CSI4_D1_P CSI_E_D1_P CSI4_D2_N CSI_F_D0_N CSI4_D2_P CSI_F_D0_P CSI4_D3_N CSI_F_D1_N CSI4_D3_P CSI_F_D1_P DSI_CLK_N CSI_G_CLK_N DSI_CLK_P CSI_G_CLK_P DSI_D0_N Camera 6 CSI_G_D0_N DSI_D0_P (2-Lane) CSI_G_D0_P DSI_D1_N CSI_G_D1_N DSI_D1_P CSI_G_D1_P NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 58...

  • Page 70: Csi Design Guidelines

    2.90 2.5 Gbps 1.92 Max trace delay / length 1 Gbps (Stripline/Microstrip) 2526 (421) / 2487 ps (mm) (421) 1.5 Gbps 1913 (319) / 1885 2.5 Gbps (319) 900 (150) / 886 (150) NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 59...

  • Page 71: Table 9-5. Mipi Csi Signal Connections

    Jetson Xavier NX). CAM[1:0]_MCLK Camera Clocks: Connect to camera reference clock inputs. GPIO01 (opt. MCLK2) GPIO11 (opt. MCLK3) CAM[1:0]_PWDN Camera Power Control signals (or GPIOs [1:0]): Connect to power down pins on camera(s). NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 60...

  • Page 72: Chapter 10. Sd Card And Sdio

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction shown in the table above for SDMMC_CLK is true when used for that function. If used as a GPIO, the pin supports input or output (bidirectional).

  • Page 73: Figure 10-1. Sd Card Connection Example

    50 (50) Topology Point to point Reference plane GND or PWR See Note 2 Trace impedance Ω ±15%. 45Ω optional depending on stack-up Max via count Independent of stack-up layers. Depends on stack-up layers. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 62...

  • Page 74: Table 10-3. Sd Card And Sdio Signal Connections

    SD Card / SDIO Command: Connect to CMD pin of device SDMMC_D[3:0] SD Card / SDIO Data: Connect to Data pins of device GPIO SD Card Detect (Optional): Connect available GPIO on module to CD pin of SD Card socket. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 63...

  • Page 75: Chapter 11. Audio

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction indicated for I2S[1:0]_DOUT and _DIN are associated with their use as I2S data lines. The direction for GPIO09 is associated with its use as Audio Clock.

  • Page 76: Figure 11-1. Audio Codec Connection Example

    I2C (see note 2) Notes: 1. The Interrupt pin from the audio codec can connect to any available Jetson Xavier NX GPIO. If the pin must be wake-capable, choose one of the GPIOs that supports this function. 2. I2C2 supports 1.8V operation since the interface is pulled to 1.8V through 2.2 kΩ resistors on the module.

  • Page 77: Table 11-3. Audio Signal Connection

    I2S Data Output: Connect to data input pin of audio device. I2S[1:0]_DIN I2S Data Input: Connect to data output pin of audio device. GPIO09 Audio Codec Clock: Connect to clock pin of audio codec. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 66...

  • Page 78: Chapter 12. Miscellaneous Interfaces

    General I2C 2 Data. 2.2kΩ pull-up to 1.8V on Open Drain – I2C2_SDA GEN1_I2C_SDA the module. 1.8V Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 67...

  • Page 79: I2C Design Guidelines

    12.1.1 I2C Design Guidelines Care must be taken to ensure I2C peripherals on same I2C bus connected to Jetson Xavier NX do not have duplicate addresses. Addresses can be in two forms: 7-bit, with the read/write bit removed or 8-bit including the read/write bit. Be sure to compare I2C device addresses using the same form (all 7-bit or all 8-bit format).

  • Page 80: Table 12-2. I2C Interface Signal Routing Requirements

    2. For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 69...

  • Page 81: Spi

    SPI #1 Device SPI1_CS1* SPI3_CS1 SPI 1 Chip Select 1 Notes: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. Figure 12-2. SPI Connections Jetson SoC – SPI...

  • Page 82: Spi Design Guidelines

    (ps) Max trace length/delay skew from MOSI, MISO and CS to SCK 16 (100) mm (ps) At any point Note: Up to four signal vias can share a single GND return via NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 71...

  • Page 83: Uart

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction indicated for the UART pins except for is true when used for that function. Otherwise, these pins support GPIO functionality and most can support both input and output (bidirectional) functionality.

  • Page 84: Figure 12-5. Uart Connections

    UART Receive: Connect to peripheral TXD pin of device UART[1:0]_CTS* UART Clear to Send: Connect to peripheral RTS pin of device UART[1:0]_RTS* UART Request to Send: Connect to peripheral CTS pin of device NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 73...

  • Page 85: Can

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction indicated for the CAN signals are associated with that usage. The pins support GPIO functionality, so support both input and output operation (bidirectional).

  • Page 86: Fan

    Notes: 1. In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. 2. The direction indicated for GPIO014 and GPIO08 is associated with their use as Fan PWM/Tach. The pins support GPIO functionality, so support both input and output operation (bidirectional).

  • Page 87: Debug

    Debug UART 1.8V UART2_TXD UART3_RX UART 2 transmit Output Note: In the Type/Dir column, Output is from Jetson Xavier NX. Input is to Jetson Xavier NX. Bidir is for Bidirectional signals. Table 12-14. Debug UART Connections Module Pin Name Type Termination...

  • Page 88: Usb Recovery Mode

    ID detection is needed. As long as the force recovery strap is held low coming out of reset, Jetson Xavier NX will configure USB0 as a device and enter recovery mode. See the USB section (Section 6.1) for an example figure that shows USB0 connected to a USB Micro B connector.

  • Page 89: Chapter 13. Pads

    Chapter 13. PADS Jetson Xavier NX signals that come from the SoC may glitch when the associated power rail is enabled. This may affect pins that are used as GPIO outputs. Designers should take this into account. GPIO outputs that must maintain a low state even while the power rail is being ramped up may require special handling.

  • Page 90: Pins Pulled Or Driven High During Power-On

    The Jetson Xavier NX is powered up before the carrier board (See Section 5.1 for power sequencing). Table 13-1 lists the pins on Jetson Xavier NX that default to being pulled or driven high. Care must be taken on the carrier board design to ensure that any of these pins that connect to devices on the carrier board (or devices connected to the carrier board) do not cause damage or excessive leakage to those devices.

  • Page 91: Table 13-2. Pins With External Pull-Ups To Supply On Before Sys_Reset* Inactive

    Table 13-2. Pins with External Pull-ups to Supply on before SYS_RESET* Inactive Jetson Xavier NX Pull-up Supply External Jetson Xavier NX Pull-up Supply External Voltage (V) Voltage (V) Pull-up (kΩ) Pull-up (kΩ) I2C0_SCL/SDA SPI1_CS0* I2C1_SCL/SDA SPI1_CS1* I2C2_SCL/SDA PCIE[1:0]_CLKREQ CAM_I2C_SCL/SDA PCIE[1:0]_RST* PCIE_WAKE*N NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 80...

  • Page 92: Chapter 14. Unused Interface Terminations

    Unused Multi-purpose Standard CMOS Pad Interfaces The following Jetson Xavier NX pins (and groups of pins) are Xavier MPIO pins that support either special function IOs (SFIO) and/or GPIO capabilities. Any unused pins or portions of pin groups listed in Table 14-1 that are not used can be left unconnected.

  • Page 93: Chapter 15. Usb 3.2 And Wireless Coexistence

    USB 3.2 connector itself. If possible, the antenna or USB 3.2 location can be changed to increase physical isolation. In general, doubling the distance between antenna and noise source, reduces the coupling by around 6 dB. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 82...
  • Page 94 USB 3.2 connectors. The shield must touch the USB 3.2 body in multiple points. The shield track must have number of grounding vias so that any emitted noise from the USB 3.2 connector is swiftly grounded. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 83...

  • Page 95: Chapter 16. Design And Bring-Up Checklists

    (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be renamed to .xlsx to open. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 84...

  • Page 96: Chapter 17. Jetson Xavier Nx Pin Descriptions

    Chapter 17. Jetson Xavier NX Pin Descriptions The Jetson Xavier NX pin description is attached to this design guide. To access the attached files, click the Attachment icon on the left-hand toolbar on this PDF (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents.

  • Page 97: Chapter 18. General Routing Guidelines

    Signal Type Codes Code Definition Analog DIFF I/O Bidirectional Differential Input/Output DIFF IN Differential Input DIFF OUT Differential Output Bidirectional Input/Output Input Output Open Drain Output I/OD Bidirectional Input / Open Drain Output Power NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 86...

  • Page 98: Routing Guideline Format

    Each interface has different trace impedance requirements and spacing to other traces. It is up to designer to calculate trace width and spacing required to achieve specified SE and Diff impedances. Unless otherwise noted, trace impedance values are ±15%. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 87...

  • Page 99: General Pcb Routing Guidelines

    Xavier NX mating connector resides) and any additional routing on a Flex/ secondary PCB segment connected to main PCB. The max length/delay should be from Jetson Xavier NX to the actual connector (i.e. USB, HDMI, etc.) or device (i.e. onboard USB device, Display driver IC, camera imager IC, etc.)

  • Page 100: Common High-Speed Interface Requirements

    Keep critical high-speed traces away from other signal traces or unrelated power traces/areas or power supply components The following figures show the common high-speed interface signal routing requirements. Figure 18-2. Common Mode Choke NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 89...

  • Page 101: Test Points For High-Speed Interfaces

     Test points should be located on the existing trace (no stub).  If the test points are placed on differential signals, they should be symmetric for each P  and N signal. NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 90...
  • Page 102 NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this document. NVIDIA accepts no liability related to any default, damage, costs, or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this document or (ii) customer product designs.

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