Table 6-10. Pcie Gen4 Interface Signal Routing Requirements - Nvidia Jetson Xavier NX Design Manual

Table 6-10. PCIe Gen4 Interface Signal Routing Requirements
Parameter
Specification
Data Rate / UI Period
Topology
Termination
Impedance
Trace Impedance
differential / Single Ended
Reference plane
Fiber-weave effect
Spacing
Trace Spacing (Stripline)
Pair – Pair
To plane and capacitor pad
To unrelated high-speed signals
Length/Skew
Trace loss budget (for carrier board routing)
Routing direct to device
Routing to PCIe/M.2 connector
Breakout region (Max Length)
Max trace length (delay)
Direct to device on carrier board
Stripline
Microstrip
Routed to PCIe or M.2 connector
Stripline
Microstrip
Max PCB via distance from the
Device/Connector
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of Vias
Max Via stub length
AC Cap
NVIDIA Jetson Xavier NX
Requirement Units
16.0 / 62.5 Gbps / ps
Point-point
43 Ω
85 / 50 Ω
GND
•
Use spread-glass (denser weave)
instead of regular-glass (sparse
weave) to minimize intra-pair skew
•
Use zig-zag route instead of
straight to minimize skew, this is a
mandatory for PCIe gen4 design
4x Dielectric
4x
4x
-16 dB
-10.5
41.9 ps
11.9 (2070) in (ps)
10.9 (1630)
7.8 (1360)
7.1 (1070)
41.9 ps
0.15 (0.5) mm (ps)
0.15 (0.5) mm (ps)
41.9 ps
Place GND vias as symmetrically as possible to data pair vias. GND via distance
should be placed less than 1x the diff pair via pitch
4
na
USB and PCIe
Notes
8.0GHz, half-rate architecture
Unidirectional, differential. Driven by
100 MHz common reference clock
To GND Single Ended for P and N
±15%
See Figure 6-15
TX and RX should not be routed on the
same layer. If this is required in a
design, they should not be interleaved,
and the spacing between the closest RX
and TX lanes must be 9x Dielectric
spacing.
@ 4GHz (See Figure 6-3),
Loss: GEN4 budget – module – end
device – safety margin (-28dB + 5dB +
4dB + 3dB)
Loss: GEN3 budget – module – end
device – safety margin (-28dB + 5dB +
9.5dB + 3dB)
Minimum width and spacing. 4x or
wider dielectric height spacing is
preferred
Mid-loss PCB of 1.47dB/in (Microstrip)
or 1.35dB/in (Stripline) is used. Also,
175ps/in for Stripline routing and
150ps/in for Microstrip.
Max distance from Device ball or
Connector pin to first PCB via.
Do trace length matching before hitting
discontinuities.
Use micro via or back drilled via - no via
stub allowed.
Not Allowed
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