Csi Design Guidelines; Figure 9-3. Available Camera Control Pins; Table 9-4. Mipi Csi Interface Signal Routing Requirements - Nvidia Jetson Xavier NX Design Manual

Figure 9-3. Available Camera Control Pins
SoC
CAM
CAM_I2C_SCL
CAM_I2C_SDA
EXTPERIPH1_CLK
SOC_GPIO04
EXTPERIPH2_CLK
SOC_GPIO05
SOC_GPIO41
SOC_GPIO42
9.1

CSI Design Guidelines

The following tables describe the design guidelines for the CSI design.
Table 9-4. MIPI CSI Interface Signal Routing Requirements
Parameter
Max Data Rate (per data lane) for High-Speed
mode
Max Frequency (for Low Power mode)
Number of loads
Reference plane
Trace impedance: Diff pair / SE
Via proximity (signal to reference)
Intra-pair trace spacing
Trace spacing: Microstrip / Stripline
Max PCB breakout delay
Max Insertion loss
1 Gbps
1.5 Gbps
2.5 Gbps
Max trace delay / length
1 Gbps (Stripline/Microstrip)
1.5 Gbps
2.5 Gbps
NVIDIA Jetson Xavier NX
Jetson
2.2kΩ
VDD_3V3_SYS
2.2kΩ
Requirement
2.5
10
1
GND
90-100 / 45-50
< 0.65 (3.8)
0.15mm
2x / 2x
48
3.00
2.90
1.92
2526 (421) / 2487
(421)
1913 (319) / 1885
(319)
900 (150) / 886
(150)
CAM_I2C_SCL
Camera
213
CAM_I2C_SDA
I2C
215
CAM0_MCLK
Camera 0
116
CAM0_PWDN
Clock/Control
114
CAM1_MCLK
Camera 1
122
CAM1_PWDN
Clock/Control
120
GPIO01
Camera 2 Clock
118
GPIO11
Camera 3 Clock
216
Units Notes
Gbps
MHz
load
Ω ±10%
mm (ps)
mm Can be adjusted to meet Differential
Impedance.
dielectric
ps
dB
ps (mm)
MIPI CSI Video Input
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