Table 6-2. Usb 3.2 And Pcie Pin Description - Nvidia Jetson Xavier NX Design Manual

Table 6-2. USB 3.2 and PCIe Pin Description
Module Pin
Pin # Xavier Signal
Name
131 PCIE0_RX0_N NVHS0_RX0_N
133 PCIE0_RX0_P NVHS0_RX0_P
137 PCIE0_RX1_N NVHS0_RX1_N
139 PCIE0_RX1_P NVHS0_RX1_P
149 PCIE0_RX2_N NVHS0_RX2_N
151 PCIE0_RX2_P NVHS0_RX2_P
155 PCIE0_RX3_N NVHS0_RX3_N
157 PCIE0_RX3_P NVHS0_RX3_P
134 PCIE0_TX0_N NVHS0_TX0_N
136 PCIE0_TX0_P NVHS0_TX0_P
140 PCIE0_TX1_N NVHS0_TX1_N
142 PCIE0_TX1_P NVHS0_TX1_P
148 PCIE0_TX2_N NVHS0_TX2_N
150 PCIE0_TX2_P NVHS0_TX2_P
154 PCIE0_TX3_N NVHS0_TX3_N
156 PCIE0_TX3_P NVHS0_TX3_P
181 PCIE0_RST* PEX_L5_RST_N
PCIE0_CLKRE PEX_L5_CLKREQ_
180
Q* N
PEX_CLK5N or
160 PCIE0_CLK_N NVHS0_REFCLK_
N
PEX_CLK5P or
162 PCIE0_CLK_P NVHS0_REFCLK_
P
167 PCIE1_RX0_N PEX_RX11_N
169 PCIE1_RX0_P PEX_RX11_P
172 PCIE1_TX0_N PEX_TX11_N
174 PCIE1_TX0_P PEX_TX11_P
183 PCIE1_RST* PEX_L4_RST_N
PCIE1_CLKRE PEX_L4_CLKREQ_
182
Q* N
173 PCIE1_CLK_N PEX_CLK4N
175 PCIE1_CLK_P PEX_CLK4P
179 PCIE_WAKE* PEX_WAKE_N
NVIDIA Jetson Xavier NX
Usage/Description
PCIe #0 Receive 0 (PCIe Ctrl #5 Lane 0)
PCIe #0 Receive 1 (PCIe Ctrl #5 Lane 1)
PCIe #0 Receive 2 (PCIe Ctrl #5 Lane 2)
PCIe #0 Receive 3 (PCIe Ctrl #5 Lane 3)
PCIe #0 Transmit 0 (PCIe Ctrl #5 Lane 0)
PCIe #0 Transmit 1 PCIe Ctrl #5 Lane 1)
PCIe #0 Transmit 2 (PCIe Ctrl #5 Lane 2)
PCIe #0 Transmit 3 (PCIe Ctrl #5 Lane 3)
PCIe #0 Reset (PCIe Ctrl #5). 4.7kΩ pull-up to
3.3V on the module. Output when module is Root
Port - input when module Endpoint.
PCIE #0 Clock Request (PCIe Ctrl #5). 47kΩ pull-
up to 3.3V on the module. Input when module is
Root Port - output when module is Endpoint.
PCIe #0 Reference Clock controlled by on-
module mux by SoC CAN0_EN. When CAN0_EN
is low, PEX_CLK5 is selected (reference clock
when module is Root Port). When CAN0_EN is
high, NVHS0_REFCLK is selected (reference
clock input when Jetson Xavier NX is an
Endpoint).
PCIe #1 Receive 0 (PCIe Ctrl #4 Lane 0)
PCIe #1 Transmit 0 (PCIe Ctrl #4 Lane 0)
PCIe #1 Reset (PCIe Ctrl #4). 4.7kΩ pull-up to
3.3V on the module.
PCIE #1 Clock Request (PCIe Ctrl #4). 47kΩ pull-
up to 3.3V on the module.
PCIe #1 Reference Clock (PCIe Ctrl #4)
PCIe Wake. 47kΩ pull-up to 3.3V on the module.
USB and PCIe
Recommended Directio
Pin Type
Usage n
Input PCIe PHY
Output PCIe PHY
PCIe x4
conn/device (i.e.
M.2 Key M)
Open
Bidir
Drain 3.3V
Bidir PCIe PHY
Input PCIe PHY
Output PCIe PHY
PCIe x1
Open
conn/device (i.e.
Output
Drain 3.3V
M.2 Key E)
Open
Bidir
Drain 3.3V
Output PCIe PHY
Shared between
Open
x1 and x4 PCIe Input
Drain 3.3V
interfaces.
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