Table 7-2. Jetson Orin Nx Usb 3.2 And Pcie Pin Description - Nvidia Jetson Orin NX Design Manual

Table 7-2. Jetson Orin NX USB 3.2 and PCIe Pin Description
Module Pin
Pin # Name Orin Signal
HS_UPHY0_L4_RX_
131 PCIE0_RX0_N
N
HS_UPHY0_L4_RX_
133 PCIE0_RX0_P
P
HS_UPHY0_L5_RX_
137 PCIE0_RX1_N
N
HS_UPHY0_L5_RX_
139 PCIE0_RX1_P
P
HS_UPHY0_L6_RX_
149 PCIE0_RX2_N
N
HS_UPHY0_L6_RX_
151 PCIE0_RX2_P
P
HS_UPHY0_L7_RX_
155 PCIE0_RX3_N
N
HS_UPHY0_L7_RX_
157 PCIE0_RX3_P
P
HS_UPHY0_L4_TX_
134 PCIE0_TX0_N
N
136 PCIE0_TX0_P HS_UPHY0_L4_TX_P
HS_UPHY0_L5_TX_
140 PCIE0_TX1_N
N
142 PCIE0_TX1_P HS_UPHY0_L5_TX_P
HS_UPHY0_L6_TX_
148 PCIE0_TX2_N
N
150 PCIE0_TX2_P HS_UPHY0_L6_TX_P
HS_UPHY0_L7_TX_
154 PCIE0_TX3_N
N
156 PCIE0_TX3_P HS_UPHY0_L7_TX_P
GP184_PCIE4_RST_
181 PCIE0_RST*
N
PCIE0_CLKRE GP183_PCIE4_
180
Q* CLKREQ_N
SF_PCIE4_CLK_N
160 PCIE0_CLK_N HS_UPHY0_
REFCLK2_N
SF_PCIE4_CLK_P
162 PCIE0_CLK_P HS_UPHY0_
REFCLK2_P
HS_UPHY0_L3_RX_
167 PCIE1_RX0_N
N
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Usage and Description
PCIe #0 Receive 0 (PCIe Ctrl #4 Lane 0)
PCIe #0 Receive 1 (PCIe Ctrl #4 Lane 1)
PCIe #0 Receive 2 (PCIe Ctrl #4 Lane 2)
PCIe #0 Receive 3 (PCIe Ctrl #4 Lane 3)
PCIe #0 Transmit 0 (PCIe Ctrl #4 Lane 0)
PCIe #0 Transmit 1 PCIe Ctrl #4 Lane 1)
PCIe #0 Transmit 2 (PCIe Ctrl #4 Lane 2)
PCIe #0 Transmit 3 (PCIe Ctrl #4 Lane 3)
PCIe #0 Reset (PCIe Ctrl #4). 4.7kΩ pull-up
to 3.3V on the module. Output when Jetson
Xavier NX is Root Port or input when
Jetson Xavier NX is Endpoint.
PCIE #0 Clock Request (PCIe Ctrl #4).
47kΩ pull-up to 3.3V on the module. Input
when Jetson Xavier NX is Root Port or
output when Jetson Rey is Endpoint.
PCIe #0 Reference Clock controlled by on-
module mux by SoC GP21. When GP21 is
low, SF_PCIE4_CLK is selected (reference
clock when module is Root Port). When
GP21 is high, UPHY0_REFCLK2_IN is
selected (reference clock input when
module is an Endpoint).
PCIe #1 Receive 0 (PCIe Ctrl #1 Lane 0)
USB and PCIe
Recommended
Usage Direction
Input
PCIe x4
conn/device (i.e.
M.2 Key M)
Output
Bidir
Bidir
Input
DG-10931-001_v0.1 | 20
Pin Type
PCIe PHY
PCIe PHY
Open
Drain 3.3V
PCIe PHY
PCIe PHY