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PCIx_PRSNT (0:1) [Hex]
5.11.6 BCSR5 and BCSR7 Board Control—Status Register 3
and 5
BCSR5 to BCSR7 are additional control / status registers which may be accessed as a word
at offset 0x14 to 0x1C from BCSR base address. These registers are not implemented.
They may be read or written but with no valid data nor any effect on the board. The
description of BCSR3 and BCSR5 is shown in Table 5-19
BIT
MNEMONIC
0 - 31
Reserved
5.12 COP/JTAG Port
The COP - Control Observation Port, is part of the PowerQUICC II's JTAG machine,
implemented as a set of additional instructions and logic within the JTAG permissions. This
port may be connected to a dedicated debug station
There are several third party debug solutions on the market. These debug-stations may be
connected to the host computer via either Ethernet, Parallel-Port, RS232 or any other
media.
The debug station connection scheme is shown in Figure 5-10.
Host
Media
Adaptor
Figure 5-10. Debug Station Connection Schemes
To support debug station connection to the COP/JTAG port, a 16 pin generic header
connector is provided on the MPC8272ADS, carrying the COP/JTAG signals as well as
1
Not provided with the MPC8272ADS.
2
3
Table 5-19. BCSR5 to BCSR7 Description
Un Implemented
Ethernet/
Parallel/
RS232/
USB...
Media
Chapter 5. Module Design
Expansion Configuration
Expansion board present, 15W maximum
No expansion board present
Function
1
, for extensive system debug.
16 Wire
Media To COP
Flat Cable
COP/JTAG Port
PON
ATT.
DEF
-
-
ADS
COP
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