Freescale Semiconductor MPC8272ADS User Manual page 55

Table 5-3. PCI Interrupt Register Description (continued)
BI
MNEMONIC
T
4 PCI1_INTA
5 PCI1_INTB
6 PCI1_INTC
7 PCI1_INTD
8 PCI2_INTA
9 PCI2_INTB
1 PCI2_INTC
0
11 PCI2_INTD
1 Reserved
2-
3
1
Also available is an interrupt mask register that provides the user with the option to mask
any of the possible PCI interrupt sources. It can be read or written at any time and accessed
at offset 0x4 from CS3 base address.The description of the PCI interrupt mask register is in
Table 5-4.
PCI Slot 1 INTA. PCI Slot 1 Interrupt A:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 1 INTB. PCI Slot 1 Interrupt B:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 1 INTC. PCI Slot 1 Interrupt C:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 1 INTD. PCI Slot 1 Interrupt D:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 2 INTA. PCI Slot 2 Interrupt A:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 2 INTB. PCI Slot 2 Interrupt B:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 2 INTC. PCI Slot 2 Interrupt C:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
PCI Slot 2 INTD. PCI Slot 2 Interrupt D:
'0' - no interrupt was requested
'1' - an interrupt was requested and waiting to be handled
Un-implemented
Chapter 5. Module Design
Reset and Reset Configuration
Function
A
PON
T
DEF
T.
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
R/
W