Freescale Semiconductor MPC8272ADS User Manual page 65

PCI Bus
The PCI bridge is implemented on the MPC8272 Local Bus. Due to PCI Standard
restrictions, no other application can reside on the local bus. The PCI bus can operate at
frequencies of 25MHz up to 66MHz @ 3.3V only. The 3.3V restriction is due to the
MPC8272 which is not 5V compliant. The PCI bus layout is shown in Figure 5-8 Special
care was taken when the layout of the MPC8272ADS was done so that the PCI standard
recommendations are followed strictly.
Main Clock
66MHz
JTAG PCI Clock
PCI
PCI Clock
PowerQUICC II
Clock
Distribution
PCI Clock
PCI Clock
CLKIN2
CLKIN1
PCI Clock
DLLOUT
PCI Bus
PCI
Arbiter
IRQ
Interrupt
Controller
Figure 5-8. PCI Bus Scheme
The clock source for the MPC8272 is main clock 100MHz clock oscillator. The PCI Clock
is derived internally from the main clock and output at DLLOUT. That clock is then
distributed to each PCI device on the bus in a way that they are all synchronized (by keeping
all clock traces the same length). The PCI Clock is also fed back to the MPC8272 for
synchronization and skew elimination purposes.
An interrupt from any PCI slot is handled by a simple generic Interrupt Controller. Each
slot can generate up to four interrupts for a total of twelve interrupts that the controller will
support. It will be made of two register mapped in a dedicated CS region. One is an
Interrupt Register (see Table 5-3) and the second is Interrupt Mask Register (see Table 5-4).
A simple priority scheme is devised to allow the controller to support more than one
interrupt concurrently.
Chapter 5. Module Design