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Table 5-2. E
Data
Field
Bus
Bits
CS10PC
24:25
ALD_EN
26
PCI_MODCK
27
1
MODCK_HI
28:31
1
Applies only ONCE after power-up reset.
The PCI configuration registers which are set at hard reset sequence are shown in Figure 5-1
Reserved
Class Code
BIST Control
MAX LAT
5.1.4
Soft Reset
Soft reset may be generated on the board from the following sources:
• COP/JTAG port
• Manual soft reset
2
PROM Hard Reset Configuration Word (continued)
Prog
Value
[Bin]
'01'
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
'0'
PCI Auto Load Enable. When high, PCI Bridge
Configuration is done automatically from the
2
FLASH/E
PROM (CPM is configuration source
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
'1'
Determines PCI clock settings as set by
PCI_MODCKH:
'0' - PCI clock set by PCI_MODCKH
'1' - PCI clock is divided according to
PCI_MODCKH
'1010'
Determines the Core's frequency out of
power-up reset.
Device ID (0x18C0)
PCI Status
Subclass Code
Header Type
PIMMR Base Address Register
Subsystem ID
Capability Pointer
/ / / / / / / /
MIN GNT
/ / / / / / / /
PCI Arbiter Control
Figure 5-1. PCI Host Configuration Registers
Chapter 5. Module Design
Reset and Reset Configuration
Implication
Vendor ID (0x1057)
PCI Command
Revision ID
Standard Programming
Latency Timer
Cache Line Size
Subsystem Vendor ID
Interrupt Pin
Interrupt Line
PCI Function
Offset In
Value
Flash
[Hex]
[Hex]
18
5A
Address
Offset (Hex)
00
04
08
0C
10
14
18
2C
34
38
3C
40
44
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