Freescale Semiconductor MPC8272ADS User Manual page 107

Table 8-4. P1—CPM Expansion Connector (continued)
Pin No. Signal Name
PC25
D7
USBCLK
D8
D9 RS_CD1# (PC23)
FETH1TXCK (PC22)
D10
ATMTFCLK (PC21)
D11
FETH1RXCK (PC21)
USBOE (PC20)
D12
D13
D14
FETH2RXCK (PC17)
D15
Attribute
USB Clock Line. When the USB port is enabled, this line is
connected to the USB clock line. When this port is disabled, this
signal is tristated and may be used for any available function of
PC24.
I/O, T.S. RS232 Port 1 Carrier Detect (L). Connected via RS232 transceiver
to RS232 DTR1# input, allowing detection of a connected terminal
to this port. This line is simply a PI/O input line to the PowerQUICC
II.
When RS232 Port 1 is disabled, this line is tristated and may be
used for any available function of PC23.
Fast-Ethernet 1Transmit Clock. When the Ethernet port is enabled,
I/O, T.S.
this clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is normally
extracted from the received data and driven to the PowerQUICC II
to qualify out coming transmit data. In Slave mode (not used with
this application) this clock should be input to the DM9161.
When the Ethernet port is disabled, this line is tristated and may be
used for any available function of PC22
ATM Transmit FIFO Clock. Upon the rising edge of this clock
I/O, T.S.
(driven by the PowerQUICC II), while the ATM port is enabled, the
cell octets are written to the PM5384's transmit FIFO. This clock
samples ATMTXD(7:0), ATMTXPTY, ATMTXEN# and ATMTSOC.
When the ATM port is disabled, this line may be used for any
available function of PC21.
I/O, T.S. Fast-Ethernet 1Receive Clock. When the Ethernet port is enabled,
this clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is extracted
from the received data and driven to the PowerQUICC II to qualify
incoming receive data.
When the Ethernet port is disabled, this line is tristated and may be
used for any available function of PC21
USB OE Line. When the USB port is enabled, this line is
connected to the OE line of the USB tranceiver. When this port is
disabled, this signal is tristated and may be used for any available
function of PC20.
Fast-Ethernet 1Receive Clock. When the Ethernet port is enabled,
I/O, T.S.
this clock (25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps) is extracted
from the received data and driven to the PowerQUICC II to qualify
incoming receive data.
When the Ethernet port is disabled, this line is tristated and may be
used for any available function of PC17
Chapter 8. Support
Interconnect Signals
Description