Texas Instruments MSP430F22x4 Series User Manual
Texas Instruments MSP430F22x4 Series User Manual

Texas Instruments MSP430F22x4 Series User Manual

Mixed signal microcontroller

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FEATURES
1
• Low Supply Voltage Range: 1.8 V to 3.6 V
23
Ultra-Low Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode: 0.7 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Internal Very-Low-Power Low-Frequency
Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Three Capture/Compare
Registers
Universal Serial Communication Interface
– Enhanced UART Supporting Auto-Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C™
10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference, Sample-
and-Hold, Autoscan, and Data Transfer
Controller
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MIXED SIGNAL MICROCONTROLLER
SLAS504G – JULY 2006 – REVISED AUGUST 2012
Two Configurable Operational Amplifiers
(MSP430F22x4 Only)
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Bootstrap Loader
On-Chip Emulation Module
Family Members Include:
– MSP430F2232
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430F2252
– 16KB + 256B Flash Memory
– 512B RAM
– MSP430F2272
– 32KB + 256B Flash Memory
– 1KB RAM
– MSP430F2234
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430F2254
– 16KB + 256B Flash Memory
– 512B RAM
– MSP430F2274
– 32KB + 256B Flash Memory
– 1KB RAM
Available in a 38-Pin Thin Shrink Small-Outline
Package (TSSOP) (DA), 40-Pin QFN Package
(RHA), and 49-Pin Ball Grid Array Package
(YFF) (See
Table
1)
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
Copyright © 2006–2012, Texas Instruments Incorporated
MSP430F22x2
MSP430F22x4

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Summary of Contents for Texas Instruments MSP430F22x4 Series

  • Page 1 MSP430x2xx Family User's Guide (SLAU144) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments.
  • Page 2 SLAS504G – JULY 2006 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 3: Dvss

    P2.5/R P1.5/TA0/TMS DVSS P1.4/SMCLK/TCK XOUT/P2.7 P1.3/TA2 XIN/P2.6 P1.2/TA1 RST/NMI/SBWTDIO P1.1/TA0 P2.0/ACLK/A0/OA0I0 P1.0/TACLK/ADC10CLK P2.1/TAINCLK/SMCLK/A1/OA0O P2.4/TA2/A4/VREF+/VeREF+/OA1I0 P2.2/TA0/A2/OA0I1 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O P3.0/UCB0STE/UCA0CLK/A5 P3.7/A7/OA1I2 P3.1/UCB0SIMO/UCB0SDA P3.6/A6/OA0I2 P3.2/UCB0SOMI/UCB0SCL P3.5/UCA0RXD/UCA0SOMI P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO AVSS P4.7/TBCLK AVCC P4.6/TBOUTH/A15/OA1I3 P4.0/TB0 P4.5/TB2/A14/OA0I3 P4.1/TB1 P4.4/TB1/A13/OA1O P4.2/TB2 P4.3/TB0/A12/OA0O Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 4: Xout/P2.7

    MSP430F22x2 Device Pinout, RHA Package 37 36 35 34 33 32 DVSS P1.1/TA0 XOUT/P2.7 P1.0/TACLK/ADC10CLK XIN/P2.6 P2.4/TA2/A4/VREF+/VeREF+ DVSS P2.3/TA1/A3/VREF−/VeREF− RST/NMI/SBWTDIO P3.7/A7 P2.0/ACLK/A0 P3.6/A6 P2.1/TAINCLK/SMCLK/A1 P3.5/UCA0RXD/UCA0SOMI P2.2/TA0/A2 P3.4/UCA0TXD/UCA0SIMO P3.0/UCB0STE/UCA0CLK/A5 P4.7/TBCLK P3.1/UCB0SIMO/UCB0SDA P4.6/TBOUTH/A15 14 15 16 17 18 19 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 5: Table Of Contents

    MSP430F22x4 Device Pinout, RHA Package 37 36 35 34 33 32 DVSS P1.1/TA0 XOUT/P2.7 P1.0/TACLK/ADC10CLK XIN/P2.6 P2.4/TA2/A4/VREF+/VeREF+/OA1I0 DVSS P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O RST/NMI/SBWTDIO P3.7/A7/OA1I2 P2.0/ACLK/A0/OA0I0 P3.6/A6/OA0I2 P2.1/TAINCLK/SMCLK/A1/OA0O P3.5/UCA0RXD/UCA0SOMI P2.2/TA0/A2/OA0I1 P3.4/UCA0TXD/UCA0SIMO P3.0/UCB0STE/UCA0CLK/A5 P4.7/TBCLK P3.1/UCB0SIMO/UCB0SDA P4.6/TBOUTH/A15/OA1I3 14 15 16 17 18 19 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 6 The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this data sheet for more details. Table 2. YFF Package Dimensions PACKAGED DEVICES MSP430F22x2 3.33 ± 0.03 mm 3.49 ± 0.03 mm MSP430F22x4 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 7 16MHz incl. 16 Registers Emulation (2BP) Timer_B3 USCI_A0: Watchdog Timer_A3 UART/LIN, JTAG Brownout WDT+ 3 CC IrDA, SPI Interface Protection 3 CC Registers, USCI_B0: 15/16− Bit Registers Shadow SPI, I2C Spy− Bi Wire RST/NMI Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 8: Xin/P2.6

    Positive reference voltage output or input General-purpose digital I/O pin P2.5/R Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator XIN/P2.6 General-purpose digital I/O pin (1) TDO or TDI is selected via JTAG instruction. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 9 Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 (2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 10: Dvss

    Spy-Bi-Wire test clock input during programming and test 38, 39 Digital supply voltage E4, E5 Analog supply voltage 1, 4 Digital ground reference Analog ground reference QFN Pad QFN package pad; connection to DV recommended. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 11 Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 P2.3/TA1/A3/ V REF- eREF- OA1I1/OA1O Negative reference voltage input OA1, analog input I1 OA1, analog output (1) TDO or TDI is selected via JTAG instruction. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 12 Timer_B, capture: CCI2A input, compare: OUT2 output (2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 13: Rst/Nmi/Sbwtdio

    Spy-Bi-Wire test clock input during programming and test 38, 39 Digital supply voltage E4, E5 Analog supply voltage 1, 4 Digital ground reference Analog ground reference QFN Pad QFN package pad; connection to DV recommended. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 14 M(R10) → M(Tab+R6) M(R10) → R11 Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 → R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source (2) D = destination Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 15 – DCO dc-generator is disabled. – ACLK remains active. • Low-power mode 4 (LPM4) – CPU is disabled. – ACLK is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – Crystal oscillator is stopped. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 16 A zero (0h) disables the erasure of the flash if an invalid password is supplied. (6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if necessary. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 17 Set via RST/NMI pin Table 11. Interrupt Flag Register 2 Address UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 18 Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 19 If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 20 G1 - P1.3 CCI2A CCR2 34 - P1.3 32 - P1.3 G1 - P1.3 ACLK CCI2B 30 - P2.4 28 - P2.4 G3 - P2.4 (internal) 38 - P1.7 36 - P1.7 D2 - P1.7 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 21 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 22 OA0I1 29 - A3 27 - A3 F3 - A3 OA1I1 OAxI1 28 - A7 26 - A7 G4 - A7 OA1I2 OAxIA 23 - A15 21 - A15 G7 - A15 OA1I3 OAxIB Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 23 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Flash Memory Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Watchdog Timer+ Watchdog/timer control WDTCTL 0120h Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 24 Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 25 Port P1 output P1OUT 021h Port P1 input P1IN 020h Special Function SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 001h SFR interrupt enable 1 000h Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 26 2.7 V 3.3 V 3.6 V Supply Voltage −V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V of 2.2 V. Figure 1. Operating Area Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 27 (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 28 = 3 V = 8 MHz = 85 °C = 25 °C = 2.2 V = 1 MHz 12.0 16.0 − Supply Voltage − V − DCO Frequency − MHz Figure 2. Figure 3. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 29 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 30 V applied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 31 (1) Alternatively, a resistive divider with two 2-kΩ resistors between V and V is used as load. The output is connected to the center tap of the divider. (2) The output voltage reaches at least 10% and 90% V at the specified toggle frequency. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 32 −10.0 −20.0 −15.0 −30.0 = 85°C −20.0 −40.0 = 85°C = 25°C = 25°C −25.0 −50.0 − High-Level Output V oltage − V − High-Level Output V oltage − V Figure 6. Figure 7. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 33 ≥ V , where V is the minimum supply voltage for the desired operating frequency. CC(min) CC(min) V CC V hys(B_IT−) V (B_IT−) CC(start) t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 34 = 3 V Typical Conditions V CC(drop) 0.001 1000 − Pulse Width − µs − Pulse Width − µs Figure 10. V Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal CC(drop) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 35 RSEL RSEL DCO(RSEL+1,DCO) DCO(RSEL,DCO) range RSEL and RSEL+1 Frequency step between tap 2.2 V, 3 V 1.05 1.08 1.12 ratio DCO(RSEL,DCO+1) DCO(RSEL,DCO) DCO and DCO+1 Duty cycle Measured at P1.4/SMCLK 2.2 V, 3 V Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 36 0°C to 85°C 11.7 12.3 CAL(12MHz) Gating time: 5 ms 3.6 V 11.7 12.3 BCSCTL1 = CALBC1_16MHZ, 15.52 16.48 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C CAL(16MHz) 3.6 V 16.48 Gating time: 2 ms Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 37 T: -40°C to 105°C Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ, 16-MHz I: -40°C to 85°C DCOCTL = CALDCO_16MHZ, 3 V to 3.6 V CAL(16MHz) calibration value T: -40°C to 105°C Gating time: 2 ms Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 38 = 25 °C 0.99 0.99 = −40 °C = 3.6 V 0.98 0.98 0.97 0.97 −50.0 −25.0 25.0 50.0 75.0 100.0 − Temperature − °C − Supply Voltage − V Figure 11. Figure 12. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 39 Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 CLOCK WAKE-UP TIME FROM LPM3 DCO FREQUENCY 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency − MHz Figure 13. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 40 = 270k = 270k 0.75 0.75 0.50 0.50 = 1M = 1M 0.25 0.25 0.00 0.00 −50.0 −25.0 25.0 50.0 75.0 100.0 − Temperature − C − Supply Voltage − V Figure 16. Figure 17. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 41 (1) Calculated using the box method: I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)] T version: [MAX(-40...105°C) - MIN(-40...105°C)]/MIN(-40...105°C)/[105°C - (-40°C)] (2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 42 (4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. (5) Measured with logic-level input frequency, but also applies to operation with crystals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 43 (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Internal: SMCLK, ACLK 2.2 V Timer_B clock frequency External: TACLK, INCLK Duty cycle = 50% ± 10% Timer_B capture timing TB0, TB1, TB2 2.2 V, 3 V TB,cap Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 44 = 20 pF (1) f = 1/2t with t ≥ max(t UCxCLK LO/HI LO/HI VALID,MO(Master) SU,SI(USCI) SU,MI(Master) VALID,SO(USCI) For the master's parameters t and t refer to the SPI parameters of the attached slave. SU,MI(Master) VALID,MO(Master) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 45 SIMO Figure 20. SPI Master Mode, CKPH = 0 1/f UCxCLK CKPL=0 UCLK CKPL=1 t LO/HI t LO/HI t HD,MI t SU,MI SOMI t VALID,MO SIMO Figure 21. SPI Master Mode, CKPH = 1 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 46 Figure 22. SPI Slave Mode, CKPH = 0 t STE,LEAD t STE,LAG 1/f UCxCLK CKPL=0 UCLK CKPL=1 t LO/HI t LO/HI t HD,SI t SU,SI SIMO t STE,ACC t VALID,SO t STE,DIS SOMI Figure 23. SPI Slave Mode, CKPH = 1 Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 47 2.2 V, 3 V µs SU,STO 2.2 V Pulse width of spikes suppressed by input filter t HD,STA t SU,STA t HD,STA 1/f SCL t SP t SU,DAT t SU,STO t HD,DAT Figure 24. I2C Mode Timing Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 48 (4) The internal reference current is supplied via terminal V . Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 49 T temperature: (MAX(-40 to 105°C) – MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C – (–40°C)) (3) The condition is that the error in a conversion started after t or t is less than ±0.5 LSB. REFON RefBuf Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 50 Turn on settling time of ADC10ON the ADC (1) The condition is that the error in a conversion started after t is less than ±0.5 LSB. The reference and input signal are already ADC10ON settled. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 51 (4) No additional current is needed. The V is used during sampling. (5) The on time, t , is included in the sampling time, t ; no additional on time is needed. VMID(on) VMID(sample) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 52 (1) ESD damage can degrade input current leakage. (2) The input bias current is overridden by the input leakage current. (3) Calculated using the box method (4) Specification valid for voltage-follower OAx configuration Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 53 −100 Medium Mode Medium Mode −150 Slow Mode −20 Slow Mode −40 −200 −60 −80 −250 1000 10000 100000 1000 10000 100000 Input Frequency − kHz Input Frequency − kHz Figure 26. Figure 27. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 54 Medium Mode, Overdrive 500 mV Slow Mode, Overdrive 10 mV Slow Mode, Overdrive 100 mV Slow Mode, Overdrive 500 mV (1) The level is not available due to the analog input voltage range of the operational amplifier. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 55 (1) This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx. (2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 56 UNIT RAM retention supply voltage CPU halted (RAMh) (1) This parameter defines the minimum supply voltage V when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 57 Supply current into TEST during fuse blow Time to blow fuse (1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 58 (I/O) I: 0; O: 1 P1.1/TA0 1 Timer_A3.CCI0A Timer_A3.TA0 P1.2 (I/O) I: 0; O: 1 P1.2/TA1 2 Timer_A3.CCI1A Timer_A3.TA1 P1.3 (I/O) I: 0; O: 1 P1.3/TA2 3 Timer_A3.CCI2A Timer_A3.TA2 (1) Default after reset (PUC/POR) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 59 P1.5 (I/O) I: 0; O: 1 P1.5/TA0/TMS 5 Timer_A3.TA0 P1.6 (I/O) I: 0; O: 1 P1.6/TA1/TDI/TCLK 6 Timer_A3.TA1 TDI/TCLK (1) X = Don't care (2) Default after reset (PUC/POR) (3) Function controlled by JTAG Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 60 CONTROL BITS/SIGNALS PIN NAME (P1.x) FUNCTION P1DIR.x P1SEL.x 4-Wire JTAG P1.7 (I/O) I: 0; O: 1 P1.7/TA2/TDO/TDI 7 Timer_A3.TA2 TDO/TDI (1) X = Don't care (2) Default after reset (PUC/POR) (3) Function controlled by JTAG Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 61 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 62: P2.1/Tainclk/Smclk/A1/Oa0O

    (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 63 P2SEL.3 OA1I1/OA1O Keeper P2IN.3 Module X IN P2IE.3 P2IRQ.3 P2IFG.3 Interrupt P2SEL.3 Edge P2IES.3 Select − OAADCx OAFCx (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 OAPMx To OA1 Feedback Network Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 64 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 65 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 66 CONTROL BITS/SIGNALS PIN NAME (P2.x) FUNCTION P2DIR.x P2SEL.x DCOR P2.5 (I/O) I: 0; O: 1 P2.5/R (1) X = Don't care (2) Default after reset (PUC/POR) (3) N/A = Not available or not applicable Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 67 P2IES.6 Select Table 29. Port P2 (P2.6) Pin Functions CONTROL BITS/SIGNALS PIN NAME (P2.x) FUNCTION P2DIR.x P2SEL.x P2.6 (I/O) I: 0; O: 1 P2.6/XIN (1) X = Don't care (2) Default after reset (PUC/POR) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 68 (2) Default after reset (PUC/POR) (3) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 69: P3.0/Ucb0Ste/Uca0Clk/A5

    3-wire SPI mode if 4-wire SPI mode is selected. (5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 70: P3.1/Ucb0Simo/Ucb0Sda

    (3) The pin direction is controlled by the USCI module. (4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode even if 4-wire SPI mode is selected. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 71: Slas504G – July 2006 – Revised August

    (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 72 (I/O) I: 0; O: 1 P4.0/TB0 0 Timer_B3.CCI0A Timer_B3.TB0 P4.1 (I/O) I: 0; O: 1 P4.1/TB1 1 Timer_B3.CCI1A Timer_B3.TB1 P4.2 (I/O) I: 0; O: 1 P4.2/TB2 2 Timer_B3.CCI2A Timer_B3.TB2 (1) Default after reset (PUC/POR) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 73 If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output, respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 74 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 75 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 76 (1) X = Don't care (2) Default after reset (PUC/POR) (3) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 77 Keeper P4IN.x Module X IN Table 38. Port P4 (Pr.7) Pin Functions CONTROL BITS/SIGNALS PIN NAME (P4.x) FUNCTION P4DIR.x P4SEL.x P4.7 (I/O) I: 0; O: 1 P4.7/TBCLK 7 Timer_B3.TBCLK (1) Default after reset (PUC/POR) Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 78 Figure 28. Fuse Check Mode Current NOTE The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information. Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 79 Port P1 (P1.0 to P1.3) Pin Functions Corrected typo in note 1 on Crystal Oscillator LFXT1, High-Frequency Mode table SLAS504G Terminal Functions tables, Corrected description of V pins. REF- eREF- Added note on TC 10-Bit ADC, Built-In Voltage Reference. REF+ Copyright © 2006–2012, Texas Instruments Incorporated...
  • Page 80 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2232IDA ACTIVE TSSOP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F2232 &...
  • Page 81 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2234TDAR ACTIVE TSSOP 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 M430F2234T &...
  • Page 82 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2254IYFFT ACTIVE DSBGA Green (RoHS SNAGCU Level-1-260C-UNLIM M430F2254 & no Sb/Br) MSP430F2254TDA ACTIVE TSSOP Green (RoHS...
  • Page 83 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2274IRHAT ACTIVE VQFN Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430 &...
  • Page 84 PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
  • Page 85 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F2232IDAR TSSOP 2000 330.0 24.4 13.0 12.0 24.0 MSP430F2232IRHAR VQFN...
  • Page 86 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F2254TRHAT VQFN 180.0 16.4 12.0 16.0 MSP430F2272IDAR TSSOP 2000 330.0 24.4 13.0 12.0 24.0 MSP430F2272IRHAR VQFN 2500 330.0...
  • Page 87 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) MSP430F2234IRHAR VQFN 2500 367.0 367.0 38.0 MSP430F2234IRHAT VQFN 210.0 185.0 35.0 MSP430F2234TRHAR VQFN 2500 367.0 367.0 38.0 MSP430F2252IDAR TSSOP 2000 367.0 367.0 45.0 MSP430F2252IRHAR VQFN 2500...
  • Page 93 D: Max = 3.518 mm, Min = 3.458 mm E: Max = 3.36 mm, Min = 3.3 mm...
  • Page 94 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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