Clock/Gate Delay Function - Agilent Technologies X Series User Manual

Figure 11-2
Clock Gate Off On
• When the
The clock signal in both "A" and "B" parts is effective and no gate function is required. Therefore,
the bit error rate is measured using the clock and data signal in both "A" and "B" parts.
Clock Gate Off On
• When the
The clock signal in "A" part is effective. Therefore, the bit error rate is measured using the clock
and data signals in "A" part.
Clock Gate Off On
• When the
The clock signal in "B" part is effective. Therefore, the bit error rate is measured using the clock
and data signals in "B" part.

Clock/Gate Delay Function

This function enables you to restore the timing relationship between the clock/gate timing as it
passes through the unit under test (UUT) and the packet data.
The shifted clock signal is emitted from pin 17 of the AUX I/O rear panel connector. When you use
the clock delay function, the clock signal to the BER CLK IN connector is delayed by the clock delay
function. When you use the gate delay function with the clock gate function, the clock signal is gated
by the gate signal which is delayed by the gate delay function.
To see the signal flow using the clock and gate functions, refer to
Agilent X-Series Signal Generators User's Guide
softkey is set to Off:
On
softkey is set to , and the
On
softkey is set to , and the
Bit Error Rate Tester–Option UN7
Clock Gate Polarity Neg Pos
Clock Gate Polarity Neg Pos
Figure 11- 3.
BERT (Option UN7)
Pos
softkey is set to :
Neg
softkey is set to :
293