Clock Source - Agilent Technologies X Series User Manual

Digital Signal Interface Module (Option 003/004)
Clock Timing
sample rate is reduced by the clocks per sample value when the value is greater than one. For an IF
signal or an input signal, clocks per sample is always set to one. Refer to
mode parallel and parallel interleaved port configuration clock rates.
Table 10-5 Output Parallel and Parallel Interleaved Clock Rates
Logic Type Signal Type
LVDS IQ
IF
Other IQ
IF
For Input mode, the maximum clock rate is limited by the following factors:
• sample size
• data type
Refer to Table 10- 6 for the Input mode parallel and parallel interleaved port configuration clock
rates.
Table 10-6 Input Parallel and Parallel Interleaved Clock Rates
Logic Type
N/A Samples
Pre- FIR Samples

Clock Source

The clock signal for the N5102A module is provided in one of three ways through the following
selections:
• Internal: generated internally in the interface module (requires an external reference)
• External: generated externally through the Ext Clock In connector
• Device: generated externally through the Device Interface connector
The clock source is selected using the N5102A module UI on the signal generator, see
256
Minimum Rate
1 x (clocks/sample) kHz
4 kHz
1 x (clocks/sample) kHz
4 kHz
Data Type
1 kHz
1 kHz
the smaller of: 100 x (clocks /sample) MHz
or
400 MHz
400 MHz
the smaller of: 100 x (clocks /sample) MHz
or
150 MHz
150 MHz
Minimum Rate
200 MHz
100 MHz
Agilent X-Series Signal Generators User's Guide
Table 10- 5 for the Output
Maximum Rate
Maximum Rate
Figure 10- 2.