I/O Pin Exceptions; User I/Os - Enclustra Mercury SA1 SoC Module User Manual

Signal Name
IO_B3A_RX<...>
IO_B3A_TX<...>
IO_B3B_RX<...>
IO_B3B_TX<...>
IO_B3B_CLK<...>
IO_B4A_RX<...>
IO_B4A_CLK<...>
IO_B4A_TX<...>
IO_B5A_RX<...>
IO_B5A_TX<...>
IO_B5B_CLK<...>
IO_B5B_TX<...>
IO_B8A_CLK<...>
IO_B8A_TX<...>
Total
Table 5: User I/Os
The IO_B3B_CLK0_B31_<...>_B32_<...> pair is connected to the two FPGA pin pairs B31 and B32. This pair
can be used either as LVDS receive using the B31 pair or as LVDS transmit using the B32 pair. The user may
only use one of these pairs, hence the FPGA design should set both pins of the unused pin pair to high
impedance in order to prevent contention. These pins are regular I/O pins for non-differential applications.
The reason for this special connection is compatibility with certain Mercury base boards.
2.9.2

I/O Pin Exceptions

The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mercury boards they may have a specific role).
Table 6 lists the I/O pin exceptions on the Mercury SA1 SoC module.
D-0000-402-002
Signals Pairs Differential
8 4 In
8 4 Out
12 6 In
14 7 Out
4 2 In
30 15 In
4 2 In
28 14 Out
8 4 In
8 4 Out
4 2 In
2 1 Out
2 1 In
2 1 Out
134 67 -
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Single-ended I/O Bank
In/Out 3A
In/Out 3A
In/Out 3B
In/Out 3B
In/Out 3B
In/Out 4A
In/Out 4A
In/Out 4A
In/Out 5A
In/Out 5A
In/Out 5B
In/Out 5B
In/Out 8A
In/Out 8A
- -
Version 06, 16.02.2021