Differential I/Os - Enclustra Mercury SA1 SoC Module User Manual

I/O Name
HPS_GPIO59_MISO
HPS_GPIO57_CLK
Table 6: I/O Pin Exceptions
When the Mercury SA1 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe
device, the PERST# signal coming from the PCIe edge connector on the module connector pin A-104
(HPS_GPIO59_MISO) is driven further to IO_B5A_RX_R6_PERST#_W15_N.
Because the PCIe block inside the FPGA logic side requires this reset signal, the PERST# signal is connected
to the FPGA pin IO_B5A_RX_R6_PERST#_W15_N via a 47 k resistor. In situations in which a custom board is
used or PCIe functionality is not required, this FPGA pin can be used in the same manner as a regular I/O pin.
The connection of the CVP pin to the PCIe WAKE# pin on the Mercury+ PE1 base board is made in a similar
manner - note that the connection is not available in the standard configuration, as not all PCIe cards support
the wake function. Details on the CVP implementation can be found in the Altera CVP documentation [23]
and details on the WAKE# pin are available in the PCIe specification.
2.9.3

Differential I/Os

When using differential pairs, a differential impedance of 100
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the SoC device to the module connector is
available in Mercury SA1 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
Warning!
Please note that the trace length of various signals may change between revisions of the Mercury SA1
SoC module. Please use the information provided in the Mercury SA1 SoC Module IO Net Length Excel
Sheet [3] to check which signals are affected. The differential signals will still be routed differentially
in subsequent product revisions.
Please note that Cyclone V devices can only use I/O pins marked with "RX" in the signal name as differential
inputs and only pins marked with "TX" as differential outputs. All pins can be used as single-ended inputs
or outputs.
Warning!
Check Mercury SA1 SoC module pinout with Quartus before producing your own base board hardware,
to make sure that all pins are used according to the correct direction.
D-0000-402-002
Module Connector Pin
A-104
A-98
Description
Connected via
IO_B5A_RX_R6_PERST#_W15_N pin (A-36) for PCIe
PERST# connection implementation
Can optionally be connected via a 47 k
IO_B5A_TX_R3_CVP_AD26_N pin (A-21) for Configura-
tion via Protocol (CVP) implementation (CVP pin can
be connected to PCIe WAKE# pin)
must be matched on the base board, and
18 / 49
a 47 k resistor
resistor to
Version 06, 16.02.2021
to