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Mercury XU5 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury XU5 SoC module to the user, and
to provide the user with a comprehensive guide to understanding and using the Mercury XU5 SoC module.
Summary
This document first gives an overview of the Mercury XU5 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-XU5
Reference
D-0000-445-001
Name
DIUN
GKOE, GLAC
DIUN
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury XU5 SoC Module
Version
07
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
25.07.2019
Date
08.06.2018
22.06.2018
25.07.2019
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Summary of Contents for Enclustra Mercury XU5
- Page 1 User Manual Purpose The purpose of this document is to present the characteristics of Mercury XU5 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury XU5 SoC module. Summary This document first gives an overview of the Mercury XU5 SoC module followed by a detailed description of its features and configuration options.
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
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Page 3: Table Of Contents
Enclustra Build Environment ........ - Page 4 3.12 Enclustra Module Configuration Tool ........54...
- Page 5 Overview ..........55 Signal Description .
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Page 6: Overview
The Enclustra Build Environment [15] is available for the Mercury XU5 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader). -
Page 7: Electrostatic Discharge
Warning! It is possible to mount the Mercury XU5 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury XU5 SoC module. -
Page 8: Deliverables
Enclustra Build Environment The Enclustra Build Environment (EBE) [15] enables the user to quickly set up and run Linux on any Enclustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL. -
Page 9: Mercury+ Pe1 Base Board
Please note that the available features depend on the equipped Mercury module type and on the selected base board variant. Xilinx Tool Support The MPSoC devices equipped on the Mercury XU5 SoC module are supported by the Vivado HL WebPACK Edition software, which is available free of charge. Please contact Xilinx for further information. D-0000-445-001 9 / 64 Version 07, 25.07.2019... -
Page 10: Module Description
Figure 2: Hardware Block Diagram - G1 Variants The main component of the Mercury XU5 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of its I/O pins are connected to the Mercury module connector, making up to 158 regular user I/Os available... - Page 11 to the user. Further, up to 8 MGT pairs are available on the module connector, making possible the imple- mentation of several high-speed protocols such as PCIe Gen3/Gen2 4 and USB 3.0 (simultaneous usage of all the interfaces is limited to the available hardware resources i.e. number of transceivers and lane mapping). The “G1”...
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Page 12: Module Configuration And Product Codes
G1 assembly variants offered for migration purposes or for cases where the end application does not require GTR transceivers, but instead more regular I/Os. It can be used when porting an existing design from Mercury ZX1 or ZX5 to Mercury XU5 SoC module. -
Page 13: Article Numbers And Article Codes
The correspondence between article number and article code is shown in Table 2. The article code repre- sents the product code, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury XU5 SoC Module Known Issues and Changes document [7]. -
Page 14: Article Numbers And Article Codes
Article Number Article Code EN101970 ME-XU5-2EG-1I-D11E-R1 EN102025 ME-XU5-3EG-2I-D11E-R1 EN102026 ME-XU5-4EV-1I-D11E-R1 EN102027 ME-XU5-5EV-2I-D12E-R1 EN102028 ME-XU5-5EV-3E-D13E-R1 EN102060 ME-XU5-5EV-2I-D12E-G1-R1 EN102596 ME-XU5-2CG-1E-D10H-R1.2 EN102224 ME-XU5-2EG-1I-D11E-R1.2 EN102225 ME-XU5-3EG-2I-D11E-R1.2 EN102598 ME-XU5-4CG-1E-D11E-G1-R1.2 EN102226 ME-XU5-4EV-1I-D11E-R1.2 EN102285 ME-XU5-4EV-1I-D11E-G1-R1.2 EN102599 ME-XU5-5EV-1E-D11E-R1.2 EN102227 ME-XU5-5EV-2I-D12E-R1.2 EN102229 ME-XU5-5EV-2I-D12E-G1-R1.2 EN102228 ME-XU5-5EV-3E-D13E-R1.2 Table 2: Article Numbers and Article Codes D-0000-445-001 14 / 64 Version 07, 25.07.2019... -
Page 15: Top And Bottom Views
Top and Bottom Views 2.4.1 Top View Figure 5: Module Top View 2.4.2 Bottom View Figure 6: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. D-0000-445-001 15 / 64 Version 07, 25.07.2019... -
Page 16: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings 2.5.1 Top Assembly Drawing Figure 7: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 8: Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. -
Page 17: Module Footprint
Figure 9: Module Footprint - Top View Warning! It is possible to mount the Mercury XU5 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury XU5 SoC module. -
Page 18: Module Connector
Symbol Value Size 54 mm Component height top 3.32 mm Component height bottom 1.35 mm Weight 26 g Table 3: Mechanical Data Module Connector Two Hirose FX10 168-pin 0.5 mm pitch headers with a total of 336 pins have to be integrated on the base board. -
Page 19: User I/O
User I/O 2.9.1 Pinout Information on the Mercury XU5 SoC module pinout can be found in the Enclustra Mercury Master Pinout [12], and in the additional document Enclustra Module Pin Connection Guidelines [11]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only. -
Page 20: I/O Pin Exceptions
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible limitations. Signal Name Sign. Pairs Differential Single- I/O Bank ended IO_B65_<...> In/Out In/Out 65 (HP) IO_B66_<...> In/Out In/Out 66 (HP) IO_BE_<...> In/Out (no LVDS/LVPECL outputs In/Out 25 (HD) for ZU2/ZU3... -
Page 21: I/O Pin Exceptions - Perst
PCIe Reset Signal (PERST#) Table 6 lists the I/O pin exceptions on the Mercury XU5 SoC module related to the PCIe reset connection. I/O Name Module Connector Pin Description PS_MIO42_PERST# A-104 When the pin has a low value, its value is routed via... -
Page 22: Assembly Options For Mgt Tx/Rx Signals
The “G1” assembly variants can be also be useful in cases where the end application does not require GTR transceivers, but instead more regular I/Os. Design support files such as the Mercury Master Pinout [12], Mercury XU5 SoC Module User Schematics [6], and Mercury XU5 SoC Module FPGA Pinout Assembly Variants Excel Sheet [5] offer additional information on assembly options and migration guidelines. -
Page 23: Assembly Options For Mgt Refclk Signals
Figure 12: Assembly Options for MGT REFCLK Signals Figure 13: Assembly Options for MIO/PL Signals Module Variant ME-XU5-2CG/2EG/3EG ME-XU5-4CG/4EV/5EV ME-XU5-4CG/4EV/5EV-G1 Compatibility XU1 (partially) ZX5 and ZX1-30 Signal Name MPSoC Pin Connectivity MGT_B224_REF- IO_B66_L11_GC_D4_P MGT_B224_REFCLK0_Y6_P IO_B66_L11_GC_D4_P CLK0_Y6_B66_L11_D4_P MGT_B224_REF- IO_B66_L11_GC_C4_N MGT_B224_REFCLK0_Y5_N IO_B66_L11_GC_C4_N CLK0_Y5_B66_L11_C4_N MGTPS_REF- IO_B66_L1_G1_P... - Page 24 Module Variant ME-XU5-2CG/2EG/3EG ME-XU5-4CG/4EV/5EV ME-XU5-4CG/4EV/5EV-G1 Compatibility XU1 (partially) ZX5 and ZX1-30 Signal Name MPSoC Pin Connectivity MGTPS_TX1_D23_MGT_ B-21 MGTPS_TX1_D23_P MGTPS_TX1_D23_P MGT_B224_TX1_U4_P B224_TX1_U4_P MGTPS_TX1_D24_MGT_ B-25 MGTPS_TX1_D24_N MGTPS_TX1_D24_N MGT_B224_TX1_U3_N B224_TX1_U3_N MGTPS_TX2_C25_MGT_ B-29 MGTPS_TX2_C25_P MGTPS_TX2_C25_P MGT_B224_TX2_R4_P B224_TX2_R4_P MGTPS_TX2_C26_MGT_ B-33 MGTPS_TX2_C26_N MGTPS_TX2_C26_N MGT_B224_TX2_R3_N B224_TX2_R3_N MGTPS_TX3_B23_MGT_ B-37 MGTPS_TX3_B23_P...
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Page 25: Differential I/Os
The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury XU5 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application. -
Page 26: Vcc_Io Usage
Bank Connectivity VCC_IO VREF Bank 64 PL DDR4 SDRAM, clock oscilla- 1.2 V 0.6 V User selectable User selectable Bank 65 Module connector , LEDs VCC_IO_B65 VCC_IO_B65 User selectable User selectable Bank 66 Module connector VCC_IO_B66 VCC_IO_B66 Bank E Gigabit Ethernet PHY 1, I2C, User selectable 25 (ZU2/ZU3) or 45 (ZU4/ZU5) module connector... - Page 27 For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per module connector. Signal Name MPSoC Pins Supported Connector Connector Voltages A Pins B Pins VCC_CFG_MIO VCCO_PSIO1_501, 1.8 V - 3.3 V 74, 77...
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Page 28: Signal Terminations
GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. Table 10 gives an overview over the MIO pin connections on the Mercury XU5 SoC module. Only the pins marked with “user functionality” are available on the module connector. -
Page 29: Analog Inputs
MIO Group Function Connection QSPI flash QSPI flash QSPI feedback clock 10-11 On-board I2C bus and module connector via level shifter I2C interrupt On-board I2C bus 13-22 eMMC flash eMMC flash 24-25 LED0#, LED1# On-board LEDs 7-9, 23 Unused 26-29, 31-37 Ethernet Gigabit Ethernet PHY 0 Ethernet/PCIe block PERST# signal... -
Page 30: Multi-Gigabit Transceiver (Mgt)
ZU4/ZU5 MPSoC devices. GTH Transceivers On modules equipped with ZU4/ZU5 there are 4 GTH MGTs available on the Mercury XU5 SoC module - Table 12 describes the connections. The naming convention for the GTH MGT I/Os is: MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>. - Page 31 GTR Transceivers There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury XU5 SoC module connected to I/O bank 505; these are routed by default to module connector B - refer to Section 2.9.2 for details on the assembly variants and MGT connectivity.
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Page 32: Power
Power Generation Overview The Mercury XU5 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages (0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector. -
Page 33: Power Enable/Power Good
Power Enable/Power Good The Mercury XU5 SoC module provides a power enable input on the module connector. This input may be used to shut down the DC/DC converters and LDOs for 0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V and 2.5 V. -
Page 34: Voltage Supply Outputs
MPSoC is adequately cooled. Table 17 lists the heat sink and thermal pad part numbers that are compatible with the Mercury XU5 SoC module. Details on these parts and additional information that may assist in selecting a suitable heat sink for the Mercury XU5 SoC module can be found in the Enclustra Modules Heat Sink Application Note [18]. -
Page 35: Voltage Monitoring
Clock Generation A 33.33 MHz oscillator is used for the Mercury XU5 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator is connected to FPGA bank 64 and can serve as a reference for the PLL used to generate the clocks required for the PL DDR interface. -
Page 36: Reset
Please note that PS_POR# is automatically asserted if PWR_GOOD is low. 2.14 LEDs There are four active-low user LEDs on the Mercury XU5 SoC module - one of them is connected to the PS, one connected to both PS and PL and two connected to the PL. D-0000-445-001 36 / 64 Version 07, 25.07.2019... -
Page 37: Ddr4 Sdram (Ps)
DDR4 SDRAM (PS) There are two DDR4 SDRAM channels on the Mercury XU5 SoC module: one attached directly to the PS side (which is available only as a shared resource to the PL side) and one attached directly to the PL side. -
Page 38: Ddr4 Sdram Type
Please check the user manual regularly for updates. Any parts with different speed bins or temperature ranges that fulfill the requirements for the module variant may be used. 2.15.2 Signal Description Please refer to the Mercury XU5 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3 Termination Warning! No external termination is implemented for the data signals on the Mercury XU5 SoC module. -
Page 39: Parameters
The values given in Table 24 are for reference only. Depending on the equipped memory device on the Mercury XU5 SoC module and on the DDR4 SDRAM frequency, the configuration may be different to the one in the reference design. Please refer to the memory device datasheet for details. -
Page 40: Ddr4 Sdram Type
Please check the user manual regularly for updates. Any parts with different speed bins or temperature ranges that fulfill the requirements for the module variant may be used. 2.16.2 Signal Description Please refer to the Mercury XU5 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.16.3 Termination Warning! No external termination is implemented on the Mercury XU5 SoC module. -
Page 41: Parameters
Table 27 describes the memory availability and configuration on the Mercury XU5 SoC module. As there is one QSPI flash chip equipped on the Mercury XU5 SoC module, type “single” must be selected when programming the flash from Vivado tools. -
Page 42: Signal Description
The eMMC flash can be used to boot the PS, and to store the FPGA bitstream, ARM application code and other user data. 2.18.1 eMMC Flash Type Table 28 describes the memory availability and configuration on the Mercury XU5 SoC module. Flash Type Size Manufacturer... -
Page 43: Signal Description
2.20 Gigabit Ethernet (PS) Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury XU5 SoC module, one connected to the PS via RGMII interface, and one connected to PL via RGMII. 2.20.1 Ethernet PHY Type Table 29 describes the equipped Ethernet PHY (PS) device type on the Mercury XU5 SoC module. -
Page 44: External Connectivity
2.20.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin Connection Guidelines [11] for details regarding the connection of Ethernet signals. 2.20.4 MDIO Address The MDIO address assigned to PHY 0 is 3, and the PHY can be configured via MIO pins 76-77. -
Page 45: Gigabit Ethernet (Pl)
Please note that the Xilinx GMII to RGMII converter cannot be used on the Mercury XU5 SoC module because this IP core includes I/O delay macros that are not supported in HD I/O banks (where the Ethernet pins are mapped). -
Page 46: Rgmii Delays Configuration
USB 2.0 Two USB 2.0 PHYs are available on the Mercury XU5 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device, while USB PHY 1 can be used only as host. -
Page 47: Display Port
USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board. Figure 15: USB 3.0 Implementation Example Warning! The USB 3.0 interface on the Mercury XU5 SoC module uses the GTR lines (MGTPS signals on module connector B), and not the USB_SSRX_P/N and USB_SSTX_P/N connections on module connector A. 2.24... -
Page 48: Real-Time Clock (Rtc)
(PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [19]. The RTC crystal pad input and crystal pad output are connected on the Mercury XU5 SoC module to a 32.768 kHz oscillator. -
Page 49: Device Configuration
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [19]. -
Page 50: Pull-Up During Configuration
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is released from reset. Violating this rule may damage the equipped MPSoC device, as well as other devices on the Mercury XU5 SoC module. Pull-Up During Configuration The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module;... -
Page 51: Power-On Reset Delay Override
Certain Xilinx tool versions support QSPI flash programming via JTAG only when JTAG boot mode is used (unavailable on the Mercury XU5 SoC module). Alternatively, the QSPI flash can be programmed in u-boot or Linux by the SPI controller in the PS or from an SPI external master. -
Page 52: Jtag On Module Connector
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury XU5 SoC module. Please note that the SD boot mode with level shifter is currently not supported. -
Page 53: Emmc Flash Programming
Certain Xilinx tools versions support QSPI flash programming via JTAG only when JTAG boot mode is used (unavailable on the Mercury XU5 SoC module). For more information, please refer to the Xilinx documen- tation [19] and support. Alternatively, the QSPI flash can be programmed in u-boot or Linux by the SPI controller in the PS or from an SPI external master. -
Page 54: Enclustra Module Configuration Tool
3.12 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [17]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation. -
Page 55: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury XU5 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 56: Secure Eeprom
An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury XU5 SoC module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1... -
Page 57: Product Information
Module Product Family Reserved Revision Product Information Mercury XU5 SoC module 0x0333 0x[XX] 0x[YY] 0x0333 [XX][YY] Table 43: Product Information Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 45) 0x08 MPSoC device speed grade... -
Page 58: Mpsoc Device Types
Value MPSoC Device Type XCZU2EG XCZU3EG XCZU4EV XCZU5EV XCZU2CG XCZU4CG Table 45: MPSoC Device Types Table 46 shows the available temperature ranges. Value Module Temperature Range Commercial Extended Industrial Table 46: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses;... -
Page 59: Operating Conditions
5 Operating Conditions Absolute Maximum Ratings Table 47 indicates the absolute maximum ratings for Mercury XU5 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [21]. -
Page 60: Recommended Operating Conditions
Recommended Operating Conditions Table 48 indicates the recommended operating conditions for Mercury XU5 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Char- acteristics Datasheet [21]. Symbol... -
Page 61: Ordering And Support
6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-445-001 61 / 64 Version 07, 25.07.2019... - Page 62 List of Figures Hardware Block Diagram ........10 Hardware Block Diagram - G1 Variants .
- Page 63 Gigabit Ethernet PHY (PL) Configuration - Bootstraps ......46 USB 2.0 PHY Type ..........46 EEPROM Type .
- Page 64 Ask Enclustra for details [4] Mercury XU5 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details [5] Mercury XU5 SoC Module FPGA Pinout Assembly Variants Excel Sheet Ask Enclustra for details [6] Mercury XU5 SoC Module User Schematics Ask Enclustra for details...
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