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Mercury+ XU1 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU1 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU1 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU1 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-XU1
Reference
D-0000-428-001
Name
DIUN
GLAC
DIUN
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury+ XU1 SoC Module
Version
13
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
15.08.2019
Date
04.05.2016
12.05.2016
15.08.2019
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Chapters
Table of Contents
Related Manuals for Enclustra Mercury+ XU1
Summary of Contents for Enclustra Mercury+ XU1
- Page 1 Mercury+ XU1 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU1 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU1 SoC module.
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
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Page 3: Table Of Contents
Enclustra Build Environment ........ - Page 4 3.13 Enclustra Module Configuration Tool ........56 I2C Communication Overview .
- Page 5 Recommended Operating Conditions ....... . . 62 Ordering and Support Ordering .
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Page 6: Overview
The Enclustra Build Environment [15] is available for the Mercury+ XU1 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader). -
Page 7: Electrostatic Discharge
Warning! It is possible to mount the Mercury+ XU1 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU1 SoC module. -
Page 8: Deliverables
Enclustra Build Environment The Enclustra Build Environment (EBE) [15] enables the user to quickly set up and run Linux on any Enclustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL. -
Page 9: Mercury+ Pe1 Base Board
Please note that the available features depend on the equipped Mercury module type and on the selected base board variant. Xilinx Tool Support The MPSoC devices equipped on the Mercury+ XU1 SoC module are supported by the Vivado HL Design Edition software, for which a paid license is required. Please contact Xilinx for further information. D-0000-428-001 9 / 66 Version 13, 15.08.2019... -
Page 10: Module Description
Figure 2: Hardware Block Diagram - G1 Variants The main component of the Mercury+ XU1 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making up to 214 regular user I/Os avail- able to the user. -
Page 11: Module Configuration And Product Codes
Five LEDs are connected to the MPSoC pins for status signaling. Module Configuration and Product Codes Table 1 describes the available standard module configurations. Custom configurations are available; please contact Enclustra for further information. D-0000-428-001 11 / 66 Version 13, 15.08.2019... -
Page 12: Product Code Fields
Figure 3: Product Code Fields Please note that for the first revision modules or early access modules, the product code may not respect entirely this naming convention. Please contact Enclustra for details on this aspect. D-0000-428-001 12 / 66... -
Page 13: Article Numbers And Article Codes
The correspondence between article number and article code is shown in Table 2. The article code repre- sents the product code, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury+ XU1 SoC Module Known Issues and Changes document [7]. -
Page 14: Article Numbers And Article Codes
Article Number Article Code EN101846 ME-XU1-9EG-1EES-D11E-R1.3 EN101918 ME-XU1-6EG-1I-D11E-R2 EN101919 ME-XU1-9EG-2I-D12E-R2 EN101920 ME-XU1-15EG-2I-D12E-R2 EN102114 ME-XU1-6EG-1I-D11E-R3 EN102115 ME-XU1-9EG-2I-D12E-R3 EN102116 ME-XU1-9EG-3E-D12E-R3 EN102117 ME-XU1-15EG-2I-D12E-R3 EN102278 ME-XU1-6EG-1I-D11E-R4 EN102279 ME-XU1-9EG-2I-D12E-R4 EN102280 ME-XU1-9EG-3E-D12E-R4 EN102281 ME-XU1-15EG-2I-D12E-R4 EN102600 ME-XU1-6CG-1E-D11E-G1-R4.1 EN102601 ME-XU1-6CG-1E-D11E-R4.1 EN102614 ME-XU1-6EG-1I-D11E-G1-R4.1 EN102372 ME-XU1-6EG-1I-D11E-R4.1 EN102602 ME-XU1-9EG-1E-D11E-G1-R4.1 EN102373 ME-XU1-9EG-2I-D12E-R4.1 EN102603 ME-XU1-9EG-2I-D12E-G1-R4.1 EN102374... -
Page 15: Top And Bottom Views
Top and Bottom Views 2.4.1 Top View Figure 5: Module Top View 2.4.2 Bottom View Figure 6: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. D-0000-428-001 15 / 66 Version 13, 15.08.2019... -
Page 16: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings 2.5.1 Top Assembly Drawing Figure 7: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 8: Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. -
Page 17: Module Footprint
Figure 9: Module Footprint - Top View Warning! It is possible to mount the Mercury+ XU1 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU1 SoC module. -
Page 18: Module Connector
Symbol Value Size 54 mm Component height top 3.42 mm Component height bottom 1.4 mm Weight 34 g Table 3: Mechanical Data Module Connector Three Hirose FX10 168-pin 0.5 mm pitch headers with a total of 504 pins have to be integrated on the base board. -
Page 19: User I/O
User I/O 2.9.1 Pinout Information on the Mercury+ XU1 SoC module pinout can be found in the Enclustra Mercury Master Pinout [12], and in the additional document Enclustra Module Pin Connection Guidelines [11]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only. -
Page 20: I/O Pin Exceptions
The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination with certain Mercury boards they may have a specific role). PCIe Reset Signal (PERST#) Table 6 lists the I/O pin exceptions on the Mercury+ XU1 SoC module related to the PCIe reset connection. I/O Name Module Connector Pin... -
Page 21: Assembly Options For Mgt Tx/Rx Signals
MIO pin. I/O Pins with Level Shifter There are four signals on the Mercury+ XU1 SoC module that are routed from the FPGA banks to the module connector via level shifters - these are presented in Table 7. -
Page 22: Assembly Options For Mgt Refclk Signals
Figure 12: Assembly Options for MGT REFCLK Signals Module Variant Standard Assembly Variant “G1” Assembly Variant Compatibility ME-XU1-R1/R2 ME-XU7/ME-XU8 Signal Name MPSoC Pin Connectivity IO_B66_Y10_B128_REFCLK0_F25_P C-69 IO_B66_Y10 MGT_B128_REFCLK0_F25_P IO_B66_N11_B128_REFCLK0_F26_N C-71 IO_B66_N11 MGT_B128_REFCLK0_F26_N IO_B66_L5_AD14_U2_B128_TX0_G27_P C-75 IO_B66_L5_AD14_U2_P MGT_B128_TX0_G27_P IO_B66_L5_AD14_U3_B128_TX0_G28_N C-77 IO_B66_L5_AD14_U3_N MGT_B128_TX0_G28_N IO_B66_L4_AD7_V2_B128_TX1_E27_P C-79 IO_B66_L4_AD7_V2_P... -
Page 23: Differential I/Os
The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury+ XU1 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application. -
Page 24: Vcc_Io Usage
3 4 5 If the Mercury+ XU1 SoC module is used in combination with a base board having only two module con- nectors, the VCC_IO_B64 pin that powers I/O bank 64 is connected to the on-board generated 1.8 V supply voltage. -
Page 25: Signal Terminations
Internal differential termination is not supported for the HD pins (banks 47, 48). All differential signal pairs from both HD banks may optionally be equipped with 100 differential termination resistors on the module. The resistor identifiers for each differential input pair can be retrieved from the Mercury+ XU1 SoC Module User Schematics [6]. Single-Ended Outputs There are no series termination resistors on the Mercury+ XU1 SoC module for single-ended outputs. -
Page 26: Multiplexed I/O (Mio) Pins
GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. Table 11 gives an overview over the MIO pin connections on the Mercury+ XU1 SoC module. Only the pins marked with “user functionality” are available on the module connector. -
Page 27: Mio Pins Connections Overview
MIO Group Default Function Second Function Connection QSPI flash Trace interface QSPI flash, debug connector QSPI feedback clock Trace interface (cont.) Debug connector Trace interface (cont.) Debug connector 10-11 On-board I2C bus and module and debug connectors via level shifter I2C interrupt PJTAG interface On-board... -
Page 28: Analog Inputs
(connected to the PL) and GTR transceivers (connected to the PS). GTH Transceivers There are 12 GTH MGTs available on the Mercury+ XU1 SoC module organized in three FPGA banks - Table 13 describes the connections. The naming convention for the GTH MGT I/Os is: MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>. -
Page 29: Mgt Pairs
GTR Transceivers There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU1 SoC module connected to I/O bank 505; these are routed to module connector B. The naming convention for the GTR MGT I/Os is: MGTPS_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>. -
Page 30: Power
Power Generation Overview The Mercury+ XU1 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages (0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector. -
Page 31: Generated Power Supplies
PS and PL operation at 0.9 V is not supported on modules revision 1 and 2 - please refer to the Mercury+ XU1 SoC Module Known Issues and Changes document [7] for details. Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins [11]. Power Converter Synchronization Starting with revision 3 modules, all switching converters used on the Mercury+ XU1 SoC module support synchronization of the switching frequency with an external clock. -
Page 32: Power Enable/Power Good
Power Enable/Power Good The Mercury+ XU1 SoC module provides a power enable input on the module connector. This input may be used to shut down the DC/DC converters and LDOs for 0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V and 2.5 V. -
Page 33: Voltage Supply Inputs
In this case, VCC_IO needs to be switched off in the manner indicated in Figure 13. 2.11.3 Voltage Supply Inputs Table 17 describes the power supply inputs on the Mercury+ XU1 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.9.5. Pin Name Module Connector Pins... -
Page 34: Power Consumption
MPSoC is adequately cooled. Table 19 lists the heat sink and thermal pad part numbers that are compatible with the Mercury+ XU1 SoC module. Details on these parts and additional information that may assist in selecting a suitable heat sink for the Mercury+ XU1 SoC module can be found in the Enclustra Modules Heat Sink Application Note [18]. -
Page 35: Voltage Monitoring
2.12 Clock Generation A 33.33 MHz oscillator is used for the Mercury+ XU1 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator and a 27 MHz CMOS oscillator provide reference clock inputs to the PS GTR bank 505. -
Page 36: Reset
2.14 LEDs There are three active-low user LEDs on the Mercury+ XU1 SoC module - two of them are connected to the PS and one is connected to the PL. The PS LED signals are shared with the debug connector trace signals on modules revisions 1 and 2. -
Page 37: Ddr4 Sdram
2.15 DDR4 SDRAM There is a single DDR4 SDRAM channel on the Mercury+ XU1 SoC module attached directly to the PS side and is available only as a shared resource to the PL side. The DDR4 SDRAM is connected to PS I/O bank 504. The memory configuration on the Mercury+ XU1 SoC module supports ECC error detection and correction;... -
Page 38: Signal Description
In custom configurations up to 8 GB of SDRAM memory may be equipped on the module. 2.15.2 Signal Description Please refer to the Mercury+ XU1 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3... -
Page 39: Qspi Flash
Table 27 describes the memory availability and configuration on the Mercury+ XU1 SoC module. As there is one QSPI flash chip equipped on the Mercury+ XU1 SoC module, type “single” must be selected when programming the flash from Vivado tools. -
Page 40: Signal Description
512 Mbit Cypress (Spansion) Table 27: QSPI Flash Type Warning! Other flash memory devices devices may be equipped in future revisions of the Mercury+ XU1 SoC module. Please check the user manual regularly for updates. 2.16.2 Signal Description The QSPI flash is connected to the PS MIO pins 0-5. Some of these signals are available on the module connector, allowing the user to program the QSPI flash from an external source. -
Page 41: Emmc Flash
16 GB Kingston Table 28: eMMC Flash Type Warning! Other flash memory devices may be equipped in future revisions of the Mercury+ XU1 SoC module. Please check the user manual regularly for updates. 2.17.2 Signal Description The eMMC flash signals are connected to the MIO pins 13-22 for 8-bit data transfer mode; some of these signals are shared with the PJTAG interface (Refer to Section 3.6.3 for details). -
Page 42: Signal Description
PHY Type Manufacturer Type KSZ9031RNX Microchip (Micrel) 10/100/1000 Mbit Table 29: Gigabit Ethernet PHYs Type 2.19.2 Signal Description PHY 0 is connected to ETH 0 controller from the PS I/O bank 501. One of the Ethernet TX data signals is shared with the PCIe reset signal (PERST#);... -
Page 43: External Connectivity
2.19.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin Connection Guidelines [11] for details regarding the connection of Ethernet signals. 2.19.4 MDIO Address The MDIO interface is shared between the two Gigabit Ethernet PHYs - these can be configured using the corresponding address. -
Page 44: Usb 2.0
USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU1 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host. -
Page 45: Usb 3.0
USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board. Figure 14: USB 3.0 Implementation Example Warning! The USB 3.0 interface on the Mercury+ XU1 SoC module uses the GTR lines (MGTPS signals on module connector B), and not the USB_SSRX_P/N and USB_SSTX_P/N connections on module connector A. 2.22... -
Page 46: Real-Time Clock (Rtc)
(PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [19]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU1 SoC module to a 32.768 kHz oscillator. -
Page 47: Debug Connector Type
Table 35: Debug Connector Type Warning! The Hirose debug connector on the Mercury+ XU1 SoC module is not polarized. Special care must be taken when connecting the breakout board to the debug connector. Connecting an external board the wrong way round on the debug connector may damage the equipped MPSoC device, as well as other devices on the Mercury+ XU1 SoC module. -
Page 48: Debug Connector Interface - Revision 1 And 2 Modules
MIO pins 0-9 must be assigned to TRACE controller in the PS settings of the Vivado project. Additionally, starting with revision 2 modules, the trace clock multiplexer must be equipped. Refer to the Mercury+ XU1 SoC Module User Schematics [6] for details. -
Page 49: Device Configuration
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [19]. -
Page 50: Module Connector C Detection
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is released from reset. Violating this rule may damage the equipped MPSoC device, as well as other devices on the Mercury+ XU1 SoC module. Module Connector C Detection Signal C_PRSNT# (pin C-167) must be connected to GND on the base board if the designed base board has three connectors. -
Page 51: Power-On Reset Delay Override
The boot mode can be selected via two signals available on the module connector and a signal available on the debug connector. Table 38 describes the available boot modes on the Mercury+ XU1 SoC module. PJTAG_EN# signal is only available on the optional debug connector. It has a 10 k pull-up resistor to VCC_CFG_MIO, therefore it may be left unconnected. -
Page 52: Jtag
Certain Xilinx tool versions support QSPI flash programming via JTAG only when JTAG boot mode is used (unavailable in the standard configurations of the Mercury+ XU1 SoC module). Alternatively, the QSPI flash can be programmed in u-boot or Linux by the SPI controller in the PS or from an SPI external master. -
Page 53: External Connectivity
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.6.3 PJTAG on Debug Connector The JTAG pins available on the debug connector are used by the ARM DAP for debugging the PS. -
Page 54: Emmc Boot Mode
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU1 SoC module. Please note that the SD boot mode with level shifter is currently not supported. -
Page 55: Emmc Flash Programming
Certain Xilinx tools versions support QSPI flash programming via JTAG only when JTAG boot mode is used (unavailable in the standard configurations of the Mercury+ XU1 SoC module). For more information, please refer to the Xilinx documentation [19] and support. Alternatively, the QSPI flash can be programmed in u- boot or Linux by the SPI controller in the PS or from an SPI external master. -
Page 56: Enclustra Module Configuration Tool
3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [17]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation, and is only avail- able starting with revision 2 modules. -
Page 57: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury+ XU1 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 58: Secure Eeprom
An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury+ XU1 SoC module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1... -
Page 59: Product Information
Module Product Family Reserved Revision Product Information Mercury+ XU1 SoC module 0x032F 0x[XX] 0x[YY] 0x032F [XX][YY] Table 45: Product Information Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 47) 0x08 MPSoC device speed grade... -
Page 60: Mpsoc Device Types
Value MPSoC Device Type XCZU9EG ES XCZU6EG XCZU9EG XCZU15EG XCZU6CG Table 47: MPSoC Device Types Table 48 shows the available temperature ranges. Value Module Temperature Range Commercial Extended Industrial Table 48: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses;... -
Page 61: Operating Conditions
5 Operating Conditions Absolute Maximum Ratings Table 49 indicates the absolute maximum ratings for Mercury+ XU1 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [21]. -
Page 62: Recommended Operating Conditions
Recommended Operating Conditions Table 50 indicates the recommended operating conditions for Mercury+ XU1 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Char- acteristics Datasheet [21]. Symbol... - Page 63 6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-428-001 63 / 66 Version 13, 15.08.2019...
- Page 64 List of Figures Hardware Block Diagram ........10 Hardware Block Diagram - G1 Variants .
- Page 65 Gigabit Ethernet PHYs Configuration - RGMII Delays ......44 USB 2.0 PHY Type ..........44 EEPROM Type .
- Page 66 Ask Enclustra for details [4] Mercury+ XU1 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details [5] Mercury+ XU1 SoC Module FPGA Pinout Assembly Variants Excel Sheet Ask Enclustra for details [6] Mercury+ XU1 SoC Module User Schematics Ask Enclustra for details...
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