Enclustra Mercury+ XU8 User Manual
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Enclustra Mercury+ XU8 User Manual

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Mercury+ XU8 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU8 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU8 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU8 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-XU8
Reference
D-0000-454-001
Name
DIUN, MMOS
GKOE, RPAU
SJOK
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury+ XU8 SoC Module
Version
09
Position
Design Engineer
Design Expert
Product Manager
Phone +41 43 343 39 43 – www.enclustra.com
Date
17.05.2023
Date
03.09.2018
10.09.2018
17.05.2023

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  • Page 1 Mercury+ XU8 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU8 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU8 SoC module.
  • Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
  • Page 3 Document History Version Date Author Comment 17.05.2023 WRUH, MGOS Updated for revision 3.0 modules: added product models, added information on voltage monitoring pins. Corrected typos, improved clarity and legibility. 06.09.2022 TKAU Updated for revision 2.2 modules: added information on discontinuation of support for power converter switching frequency synchronisation, changes on base board descrip- tions 16.02.2021...

  • Page 4: Table Of Contents

    Enclustra Build Environment ........
  • Page 5 3.13 Enclustra Module Configuration Tool ....... . . 53 I2C Communication Overview .
  • Page 6 I2C Address Map ..........54 Secure EEPROM .

  • Page 7: Overview

    The Enclustra Build Environment [16] is available for the Mercury+ XU8 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).

  • Page 8: Safety Recommendations And Warnings

    1.1.7 Electromagnetic Compatibility The Mercury+ XU8 SoC module is a Class A product (as defined in IEC 61000-3-2 standard) and is not intended for use in domestic environments. The product may cause electromagnetic interference, for which appropriate measures must be taken.

  • Page 9: Deliverables

    Enclustra Build Environment The Enclustra Build Environment (EBE) [16] enables the user to quickly set up and run Linux on any En- clustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL.

  • Page 10: Petalinux Bsp

    1.3.3 Petalinux BSP The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the Enclustra SoC module or system board. The documentation [18] describes the build process in detail and allows a user without Petalinux knowl- edge to build and run the desired design on the target hardware.

  • Page 11: Xilinx Tool Support

    Xilinx Tool Support The MPSoC devices assembled on the Mercury+ XU8 SoC module are supported by the Vivado HL Web- Pack Edition software, which is available free of charge. Contact Xilinx for further information. D-0000-454-001 11 / 63 Version 09, 17.05.2023...

  • Page 12: Module Description

    Block Diagram Figure 1: Hardware Block Diagram The main component of the Mercury+ XU8 SoC module is the Xilinx Zynq UltraScale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making 136 regular user I/Os available to the user.

  • Page 13: Module Configuration And Product Models

    Module Configuration and Product Models Table 1 describes the available standard module configurations. The product model indicates the module type and main features. Figure 2 describes the fields within the product model. Custom configurations are available. Contact Enclustra for more information. Product Model MPSoC...

  • Page 14: En-Numbers And Product Models

    For the first revision modules or early access modules, the product model may not respect entirely this naming convention. Contact Enclustra for more information. EN-Numbers and Product Models Every product is uniquely labeled, showing the EN-number and serial number. An example is presented in Figure 3.

  • Page 15: Numbers And Product Models

    EN-Number Product Model Revision Number EN105198 ME-XU8-7EV-2I-D12E R2.2 EN105196 ME-XU8-7EV-1E-D11E R2.2 EN105195 ME-XU8-5EV-1I-D12E R2.2 EN105187 ME-XU8-4CG-1I-D11E R2.2 EN105185 ME-XU8-4CG-1E-D11E R2.2 EN105067 ME-XU8-7EV-2E-D13E R3.0 EN104509 ME-XU8-7EG-2I-D11E R3.0 EN104467 ME-XU8-5EV-1I-D12E-NE R3.0 EN104466 ME-XU8-7EV-2I-D12E-E1 R3.0 EN104465 ME-XU8-7EV-2I-D12E R3.0 EN104464 ME-XU8-7EV-1E-D11E R3.0 EN104463 ME-XU8-5EV-1I-D12E R3.0 EN104462 ME-XU8-4CG-1I-D11E...

  • Page 16: Top And Bottom Views

    Top and Bottom Views Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View D-0000-454-001 16 / 63 Version 09, 17.05.2023...

  • Page 17: Top And Bottom Assembly Drawings

    Top and Bottom Assembly Drawings Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.5.1 Top Assembly Drawing R1820 C1900 C1902 Q1502 U500 R1607 R1609 U1702 R1823 R1824 L1700 C710 U1901 L1900 C1838 U1301...

  • Page 18: Module Footprint And Mechanical Data

    Figure 8 shows the dimensions of the module footprint on the base board. Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74 mm and having different topologies for the mounting holes. If different module types shall be fixed on the base board by screws, additional mounting holes may be required to accommodate different modules.

  • Page 19: Module Connector

    Ensure that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU8 SoC module. Table 3 describes the mechanical characteristics of the Mercury+ XU8 SoC module. A 3D model (PDF) and a STEP 3D model are available [8], [9].

  • Page 20: User I/O

    2.8.1 Pinout Information on the Mercury+ XU8 SoC module pins can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. The pin types on the schematic of the module connector and in the Master Pinout document are for reference only.

  • Page 21: I/O Pin Exceptions

    The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combi- nation with certain Mercury boards they may have a specific role). PCIe Reset Signal (PERST#) Table 6 lists the I/O pin exceptions on the Mercury+ XU8 SoC module related to the PCIe reset connection. I/O Name Module Connector Pin...

  • Page 22: Differential I/Os

    MIO30/42 does not apply in this case). I/O Pins with Level Shifter There are four signals on the Mercury+ XU8 SoC module that are routed from the FPGA banks to the module connector via level shifters - these are presented in Table 7.

  • Page 23: I/O Banks

    used; LVDS/LVPECL outputs are not supported. Internal differential termination is not supported for the HD pins; all differential signal pairs from both HD banks may optionally be equipped with 100 differential termination resistors on the module. Refer to Section 2.8.6 for details. 2.8.4 I/O Banks Table 8 describes the main attributes of the Programmable Logic (PL) and Processing System (PS) I/O...

  • Page 24: Vcc_Io Usage

    VCC_IO_B[x], respectively VCC_CFG_[x] pins. All VCC_IO_B[x] or VCC_CFG_[x] pins of the same bank must be connected to the same voltage. For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per module connector.
  • Page 25 C are used on other Enclustra modules; for compatibility purposes it is acceptable to power these pins even if they are not used on the Mercury+ XU8 SoC module. The Mercury+ XU8 SoC module may be used in combination with base boards having only two module D-0000-454-001 25 / 63 Version 09, 17.05.2023...

  • Page 26: Signal Terminations

    GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. Table 10 gives an overview over the MIO pin connections on the Mercury+ XU8 SoC module. Only the pins marked with “user functionality” are available on the module connector.

  • Page 27: Analog Inputs

    MIO Group Function Connection QSPI flash QSPI flash QSPI feedback clock Unused 10-11 On-board I2C bus and module connector via level shifter I2C interrupt On-board I2C bus 13-22 eMMC flash eMMC flash USB PHY 1 reset USB 2.0 PHY 1 24-25 LED0#, LED1# On-board LEDs...

  • Page 28: Multi-Gigabit Transceiver (Mgt)

    For optimal performance of high-speed interfaces, for example, PCIe, use redrivers on the base board. The maximum data rate on the MGT lines on the Mercury+ XU8 SoC module depends on the routing path for these signals. When using MGTs at high performance rates, ensure adequate signal integrity over the full signal path.

  • Page 29: Mgt Pairs

    There are 16 GTH MGTs available on the Mercury+ XU8 SoC module organized in four FPGA banks - Table 12 describes the connections. The GTH banks are numbered differently depending on the MPSoC device assembled on the module: MGT bank A represents:...

  • Page 30: Power

    Power Generation Overview The Mercury+ XU8 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages (0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector.

  • Page 31: Power Enable/Power Good

    1.8 V and 2.5 V. The list of regulators that can be disabled via PWR_EN signal is provided in Section 2.10.1. The PWR_EN input is pulled to VCC_3V3 on the Mercury+ XU8 SoC module with a 4.7 k resistor . The PWR_GOOD signal is pulled to VCC_3V3 on the Mercury+ XU8 SoC module with a 4.7 k resistor...

  • Page 32: Voltage Supply Inputs

    2.10.3 Voltage Supply Inputs Table 15 describes the power supply inputs on the Mercury+ XU8 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.8.5. Prior to revision 3.0, a 10 k resistor was used.

  • Page 33: Voltage Supply Outputs

    Battery voltage for MPSoC battery-backed RAM and battery-backed RTC Table 15: Voltage Supply Inputs 2.10.4 Voltage Supply Outputs Table 16 presents the supply voltages generated on the Mercury+ XU8 SoC module, that are available on the module connector. Pin Name Module Connector Pins Voltage...

  • Page 34: Heat Dissipation

    For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It rep- resents an optimal solution to cool the Mercury+ XU8 SoC module - the heat sink body is low profile and usually covers the whole module top surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB.

  • Page 35: Clock Generation

    Clock Generation A 33.33 MHz oscillator is used for the Mercury+ XU8 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator is connected to FPGA bank 65 and can serve as a reference for the PLL used to generate the clocks required for the PL DDR interface.

  • Page 36: Reset

    Note that PS_POR# is automatically asserted if PWR_GOOD is low. 2.13 LEDs There are three active-low user LEDs on the Mercury+ XU8 SoC module - two of them are connected to the PS and one connected to the PL. Prior to revision 3.0, 10 k resistors were used.

  • Page 37: Ddr4 Sdram (Ps)

    DDR4 SDRAM (PS) There are two DDR4 SDRAM channels on the Mercury+ XU8 SoC module: one attached directly to the PS side (which is available only as a shared resource to the PL side) and one attached directly to the PL side.

  • Page 38: Signal Description

    2.14.2 Signal Description Refer to the Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.14.3 Termination No external termination is implemented for the data signals on the Mercury+ XU8 SoC module. Enclus- tra strongly recommends enabling the on-die termination (ODT) feature of the DDR4 SDRAM device.

  • Page 39: Ddr4 Sdram (Pl)

    16 bit Table 26: DDR4 SDRAM (PL) Characteristics 2.15.2 Signal Description Refer to the Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3 Termination No external termination is implemented for the data signals on the Mercury+ XU8 SoC module. Enclus- tra strongly recommends enabling the on-die termination (ODT) feature of the DDR4 SDRAM device.

  • Page 40: Qspi Flash

    Table 28 describes the memory availability and configuration on the Mercury+ XU8 SoC module. As there is one QSPI flash chip assembled on the Mercury+ XU8 SoC module, type “single” must be selected when programming the flash from Vivado tools.

  • Page 41: Configuration

    The Mercury+ XU8 SoC module is equipped with a 16 GB eMMC flash. Different flash memory devices may be assembled in future revisions of the Mercury+ XU8 SoC module. Any flash memory with a different speed and temperature range fulfilling the requirements of the module variant may be used.

  • Page 42: Dual Gigabit Ethernet

    VCC_CFG_MIO must be set to 1.8 V. Note that this boot mode has not been tested, but it may be supported in the future. 2.19 Dual Gigabit Ethernet Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury+ XU8 SoC module, both connected to the PS via RGMII interfaces. 2.19.1 Ethernet PHY Characteristics Table 29 describes the Ethernet PHY devices assembled on the Mercury+ XU8 SoC module.

  • Page 43: External Connectivity

    Ethernet PHYs is connected to the I2C interrupt line, available on MIO pin 12. 2.19.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Refer to the Enclustra Module Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals. 2.19.4...

  • Page 44: Rgmii Delays Configuration

    USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU8 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device, while USB PHY 1 can be used only as host.

  • Page 45: Usb 3.0

    USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board. The USB 3.0 interface on the Mercury+ XU8 SoC module uses the GTR lines (MGTPS signals on module connector B), and not the USB_SSRX_P/N and USB_SSTX_P/N connections on module connector A.

  • Page 46: Real-Time Clock (Rtc)

    (PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU8 SoC module to a 32.768 kHz oscillator.

  • Page 47: Device Configuration

    3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [21].

  • Page 48: Module Connector C Detection

    VCC_IO pins on connector C are not used, C_PRSNT# does not influence the behavior of the module. For compatibility with other Enclustra modules, it is recommended to connect C_PRSNT# to GND on the base board if the designed base board has three connectors.

  • Page 49: Power-On Reset Delay Override

    The boot mode can be selected via two signals available on the module connector. Table 36 describes the available boot modes on the Mercury+ XU8 SoC module. Starting with revision 2, JTAG boot mode has been introduced to increase the usability with Xilinx tools, which may report issues when programming the on-board QSPI flash or when loading the FPGA bitstream in a non-JTAG boot mode.

  • Page 50: Jtag

    BOOT BOOT Mode Description Remarks MODE1 MODE0 Straps [3:0] 0110 Boot from eMMC flash 1110 Boot from SD card (with an Not supported (may be external SD 3.0 compliant supported in the future) level shifter; only available when VCC_CFG_MIO is 1.8 V) 0010 Boot from QSPI flash 0101...

  • Page 51: External Connectivity

    The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.6.3 JTAG Boot Mode Starting with revision 2, support for JTAG boot mode has been added to increase the usability of the module with Xilinx tools, for example for QSPI flash programming or FPGA bitstream loading.

  • Page 52: Emmc Boot Mode

    In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU8 SoC module. The SD boot mode with level shifter is currently not supported.

  • Page 53: Qspi Flash Programming From An External Spi Master

    3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [19]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation.

  • Page 54: I2C Communication

    4 I2C Communication Overview The I2C bus on the Mercury+ XU8 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus.

  • Page 55: Secure Eeprom

    Secure EEPROM The secure EEPROM is used to store the module serial number and configuration. An example demon- strating how to read the module information from the EEPROM memory is included in the Mercury+ XU8 SoC module reference design. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void.

  • Page 56: Module Configuration

    Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 44) 0x08 MPSoC device speed grade Temperature range See temperature range table (Table 45) Power grade 0 (Normal) 1 (Low power) 0x09 Gigabit Ethernet port count RTC assembled Reserved Reserved...

  • Page 57: Module Temperature Range

    Value Module Temperature Range Commercial Extended Industrial Table 45: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses; only the lower one is stored in the EEPROM. D-0000-454-001 57 / 63 Version 09, 17.05.2023...

  • Page 58: Operating Conditions

    5 Operating Conditions Absolute Maximum Ratings Table 46 indicates the absolute maximum ratings for Mercury+ XU8 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23].

  • Page 59: Recommended Operating Conditions

    Recommended Operating Conditions Table 47 indicates the recommended operating conditions for Mercury+ XU8 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Parameter Description Rating...

  • Page 60: Ordering And Support

    6 Ordering and Support Ordering Use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-454-001 60 / 63 Version 09, 17.05.2023...
  • Page 61 List of Figures Hardware Block Diagram ........12 Product Model Fields .
  • Page 62 Boot Modes ..........50 JTAG Interface - PL and PS Access and Debug .
  • Page 63 [1] Enclustra General Business Conditions http://www.enclustra.com/en/products/gbc/ [2] Mercury+ XU8 SoC Module Reference Design https://github.com/enclustra [3] Mercury+ XU8 SoC Module IO Net Length Excel Sheet Ask Enclustra for details [4] Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details...

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