I/O Banks - Enclustra Mercury SA1 SoC Module User Manual

2.9.4

I/O Banks

Table 7 describes the main attributes of the FPGA and Hard Processing System (HPS) I/O banks, and indicates
which peripherals are connected to each I/O bank. All I/O pins within a particular I/O bank must use the
same I/O (VCC_IO) and reference (VREF) voltages.
Bank Connectivity
MGT Bank L0 Module connector
MGT Bank L1 Module connector
Bank 3A Module connector
Bank 3B Module connector
Bank 4A Module connector
Bank 5A Module connector
Bank 5B Module connector
Bank 8A Module connector, LEDs
HPS Bank 6A DDR3L SDRAM
HPS Bank 6B DDR3L SDRAM
Configuration, I2C, LEDs,
HPS Bank 7A
module connector
HPS Bank 7B Ethernet PHY, QSPI flash
Gigabit Ethernet PHY,
configuration signals,
HPS Bank 7C
eMMC flash, module
connector
HPS Bank 7D USB PHY
Table 7: I/O Banks
D-0000-402-002
VCC_IO
1.1 V
1.1 V
User selectable
VCC_CFG_HPS_B3A_B8A
User selectable
VCC_IO_B3B_B4A
User selectable
VCC_IO_B3B_B4A
User selectable
VCC_IO_B5A_B5B
User selectable
VCC_IO_B5A_B5B
User selectable
VCC_CFG_HPS_B3A_B8A
1.35 V
1.35 V
User selectable
VCC_CFG_HPS_B3A_B8A
User selectable
VCC_CFG_HPS_B3A_B8A
User selectable
VCC_CFG_HPS_B3A_B8A
User selectable
VCC_CFG_HPS_B3A_B8A
19 / 49
VREF
-
-
0 V
0.5 VCC_IO_B3B_B4A
0.5 VCC_IO_B3B_B4A
0.5 VCC_IO_B5A_B5B
0.5 VCC_IO_B5A_B5B
0.5 VCC_CFG_HPS_B3A_B8A
0.68 V
0.68 V
0 V
0 V
0 V
0 V
Version 06, 16.02.2021